Hybrid gate cut for stacked transistors
Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.
1. A method of forming a semiconductor device, comprising:
forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets;
forming a second stack of nanosheets in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets;
forming a lower gate cut structure between the lower first nanosheets and the lower second nanosheets;
forming a gate stack on the first and second stack of nanosheets and over the lower gate cut structure after forming the lower gate cut structure; and
forming an upper gate cut structure after forming the gate stack.
2. The method of claim 1 , wherein forming the upper gate structure includes etching through the upper second nanosheets.
3. The method of claim 1 , wherein the first stack of nanosheets includes first sacrificial layers and first channel layers and the second stack of nanosheets includes second sacrificial layers and second channel layers.
4. The method of claim 3 , further comprising growing additional sacrificial material from the first stack of nanosheets and the second stack of nanosheets.
5. The method of claim 4 , wherein forming the lower gate structure includes depositing dielectric material in a space between the first stack of nanosheets and the second stack of nanosheets, after growing the additional sacrificial material.
6. The method of claim 5 , further comprising etching away the additional sacrificial material and the sacrificial layers of the first stack of nanosheets and the second stack of nanosheets before forming the gate stack.
7. The method of claim 1 , wherein forming the gate stack includes:
depositing a first work function metal layer on the upper first nanosheet and the upper second nanosheet; and
etching the first work function metal layer back to expose the upper first nanosheets and the upper second nanosheets to form a lower work function metal layer.
8. The method of claim 7 , wherein forming the gate stack includes forming dielectric plugs between the lower work function metal layer and the lower gate cut structure.
9. The method of claim 8 , further comprising etching away first work function metal layer remnants from between the upper first nanosheet stacks and from between the upper second nanosheet stacks after forming the dielectric plugs.
10. A method of forming a semiconductor device, comprising:
forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets;
forming a second stack of nanosheets in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets;
forming a lower gate cut structure between the lower first nanosheets and the lower second nanosheets;
forming a gate stack on the first and second stack of nanosheets and on the lower gate cut structure after forming the lower gate cut structure, including:
depositing a first work function metal layer on the upper first nanosheets and the upper second nanosheets;
etching the first work function metal layer back to expose the upper first nanosheets and the upper second nanosheets to form a lower work function metal layer;
forming dielectric plugs between the lower work function metal layer and the lower gate cut structure; and
depositing a second work function metal layer on the upper first nanosheets and the upper second nanosheets; and
forming an upper gate cut structure after forming the gate stack.
11. A semiconductor device, comprising:
a first stack of channel layers in a first region, the first stack of channels including upper first channels and lower first channels;
a second stack of channel layers in a second region, the second stack of channels including upper second channels and lower second channels;
a lower gate cut structure between the lower first channels and the lower second channels and not between the upper first channels and upper second channels; and
a shared gate that makes electrical contact with the upper and lower first nanosheets and the upper second nanosheets.
12. The semiconductor device of claim 11 , further comprising an upper gate cut structure that penetrates the upper second channels.
13. The semiconductor device of claim 11 , wherein the first stack of channel layers includes a first isolation dielectric layer between the upper first channels and the lower first channels.
14. The semiconductor device of claim 13 , wherein the first isolation dielectric layer includes a central dielectric material, a gate dielectric material surrounding the central dielectric material, and dielectric plugs on sidewalls of the gate dielectric material.
15. The semiconductor device of claim 13 , wherein a top surface of the lower gate cut structure has a height that reaches at least a height of a bottom surface of the first isolation dielectric layer.
16. The semiconductor device of claim 11 , wherein the first stack includes a first work function metal around the first lower channel layers and a second work function metal around the first upper channel layers.
17. The semiconductor device of claim 16 , wherein a portion of the first work function metal is between the first lower channel layers and the lower gate cut structure.
18. The semiconductor device of claim 16 , wherein the first work function metal has a first polarity and the second work function metal has a second polarity, opposite to the first polarity.
19. The semiconductor device of claim 11 , wherein the first isolation dielectric layer has a height that does not reach a height of the first upper channel layers.
20. The semiconductor device of claim 11 , further comprising a gate cut structure that penetrates from a top surface of the shared gate to an underlying substrate.