Backside illumination type solid-state imaging device, manufacturing method for backside illumination type solid-state imaging device, imaging apparatus and electronic equipment
The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
1. A semiconductor device comprising:
a first section including:
a first semiconductor element including a first semiconductor substrate and a first multilayer wiring layer; and
a second section including:
a second semiconductor element including a second semiconductor substrate and a second multilayer wiring layer; and
a third semiconductor element including a third semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second semiconductor element are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other,
wherein the first semiconductor element and the third semiconductor element are bonded together such that the first multilayer wiring layer and the third multilayer wiring layer face each other,
wherein a size of the first semiconductor element is larger than a size of the second semiconductor element and a size of the third semiconductor element,
wherein the size of the second semiconductor element is larger than the size of the third semiconductor element,
wherein a center point of each of the first semiconductor element, the second semiconductor element and the third semiconductor element is aligned,
wherein the first, second, and third multilayer wiring layers include a plurality of terminals,
wherein the plurality of terminals of the first and second multilayer wiring layers are directly bonded,
wherein the plurality of terminals of the first and third multilayer wiring layers are directly bonded, and
wherein the first semiconductor element is disposed between the second and third semiconductor elements.
2. The semiconductor device according to claim 1 , wherein the first semiconductor element is larger than the second semiconductor element.
3. The semiconductor device according to claim 1 , wherein the first semiconductor element is smaller than the second semiconductor element.
4. The semiconductor device according to claim 1 , wherein signal processing circuits necessary for signal processing of a pixel signal are embedded by an embedding member,
wherein the signal processing circuits are laid out such that a gap between the signal processing circuits is minimized, and the gap is filled with the embedding member, wherein the signal processing circuits include a first signal processing circuit and a second signal processing circuit, and wherein the second semiconductor element has therein the first signal processing circuit and the second signal processing circuit arranged in a juxtaposed relation in a horizontal direction and embedded by the embedding member.
5. The semiconductor device according to claim 1 , further comprising:
a first terminal on the first semiconductor element connected by a wire to a second terminal on the second semiconductor element, wherein the wire electrically connects the first semiconductor element and the second semiconductor element through a through-via,
wherein the first semiconductor element and the second semiconductor element are stacked by oxide film joining.
6. The semiconductor device according to claim 5 , wherein the wire is joined by CuCu joining.
7. The semiconductor device according to claim 5 , wherein the wire electrically connects the first semiconductor element and the second semiconductor element through the through-via formed from an imaging face side of the semiconductor device.
8. The semiconductor device according to claim 5 , wherein the wire electrically connects the first semiconductor element and the second semiconductor element through the through-via formed from a face on an opposite side to an imaging face of the semiconductor device.
9. The semiconductor device according to claim 4 , wherein the embedding member includes an oxide film.
10. The semiconductor device according to claim 4 , wherein the embedding member includes an organic material.
11. The semiconductor device according to claim 4 , wherein the second semiconductor element includes a dummy circuit configured from a semiconductor element and includes a dummy wire embedded by the embedding member.
12. The semiconductor device according to claim 1 ,
wherein a heat dissipation member that includes a member having a thermal conductivity higher than a predetermined thermal conductivity and dissipates heat is stacked on a face of the second semiconductor element opposite to a face on which the first semiconductor element is stacked.
13. The semiconductor device according to claim 12 , wherein the heat dissipation member includes SiC, AlN, SIN, Cu, Al, and C.
14. The semiconductor device according to claim 12 , wherein the heat dissipation member includes a waterway for circulating cooling water.
15. The semiconductor device according to claim 4 ,
wherein the signal processing circuits include a logic circuit, a memory circuit, a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.
16. The semiconductor device according to claim 4 ,
wherein the signal processing circuits are each embedded by the embedding member after being joined to the second semiconductor element beginning with a portion around a contacted portion.
17. The semiconductor device according to claim 16 , wherein the portion includes an end side and an end point of each signal processing circuit.
18. The semiconductor device according to claim 16 , wherein each signal processing circuit is smaller than the first semiconductor element.
19. The semiconductor device according to claim 16 , wherein the portion includes an end side and an end point of the signal processing circuit.
20. A manufacturing method for a semiconductor device that includes:
a first section including:
a first semiconductor element including a first semiconductor substrate at and a first multilayer wiring layer; and
a second section including:
a second semiconductor element including a second semiconductor substrate and a second multilayer wiring layer; and
a third semiconductor element including a third semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second semiconductor element are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other,
wherein the first semiconductor element and the third semiconductor element are bonded together such that the first multilayer wiring layer and the third multilayer wiring layer face each other,
wherein a size of the first semiconductor element is larger than a size of the second semiconductor element and a size of the third semiconductor element,
wherein the size of the second semiconductor element is larger than the size of the third semiconductor element,
wherein a center point of each of the first semiconductor element, the second semiconductor element and the third semiconductor element is aligned,
wherein the first, second, and third multilayer wiring layers include a plurality of terminals,
wherein the plurality of terminals of the first and second multilayer wiring layers are directly bonded,
wherein the plurality of terminals of the first and third multilayer wiring layers are directly bonded, and
wherein the first semiconductor element is disposed between the second and third semiconductor elements.
21. An imaging apparatus comprising:
a semiconductor device that includes:
a first section including:
a first semiconductor element including a first semiconductor substrate at a first side and a first multilayer wiring layer at a second side that is an opposite side of the first side; and
a second section including:
a second semiconductor element including a second semiconductor substrate and a second multilayer wiring layer; and
a third semiconductor element including a third semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second semiconductor element are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other,
wherein the first semiconductor element and the third semiconductor element are bonded together such that the first multilayer wiring layer and the third multilayer wiring layer face each other,
wherein a size of the first semiconductor element is larger than a size of the second semiconductor element and a size of the third semiconductor element,
wherein the size of the second semiconductor element is larger than the size of the third semiconductor element,
wherein a center point of each of the first semiconductor element, the second semiconductor element and the third semiconductor element is aligned,
wherein the first, second, and third multilayer wiring layers include a plurality of terminals,
wherein the plurality of terminals of the first and second multilayer wiring layers are directly bonded,
wherein the plurality of terminals of the first and third multilayer wiring layers are directly bonded, and
wherein the first semiconductor element is disposed between the second and third semiconductor elements.
22. Electronic equipment comprising:
a semiconductor device that includes:
a first section including:
a first semiconductor element including a first semiconductor substrate at a first side and a first multilayer wiring layer at a second side that is an opposite side of the first side; and
a second section including:
a second semiconductor element including a second semiconductor substrate and a second multilayer wiring layer; and
a third semiconductor element including a third semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second semiconductor element are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other,
wherein the first semiconductor element and the third semiconductor element are bonded together such that the first multilayer wiring layer and the third multilayer wiring layer face each other,
wherein a size of the first semiconductor element is larger than a size of the second semiconductor element and a size of the third semiconductor element,
wherein the size of the second semiconductor element is larger than the size of the third semiconductor element,
wherein a center point of each of the first semiconductor element, the second semiconductor element and the third semiconductor element is aligned,
wherein the first, second, and third multilayer wiring layers include a plurality of terminals,
wherein the plurality of terminals of the first and second multilayer wiring layers are directly bonded,
wherein the plurality of terminals of the first and third multilayer wiring layers are directly bonded, and
wherein the first semiconductor element is disposed between the second and third semiconductor elements.