Method for manufacturing an optical switching system
A method for manufacturing an optical system, the method includes obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate.
1. A method for manufacturing an optical system, the method comprises:
obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and
performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate,
wherein the first switching cell comprises: a first port, a second port, a third port, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment, and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide; wherein the performing of the CMOS compliant operations processes comprises etching the stack of layers by an etching process that exhibits a higher etching rate of the silicon alloy layers in comparison to an etching rate of the monocrystalline silicon layer.
2. The method according to claim 1 , wherein the etching is preceded by forming etch material conduits, and the etching comprises using the etch material conduits to convey etch materials that etch the stack of layers.
3. The method according to claim 2 , wherein the material conduits have a diameter that ranges between 0.5 to 2 microns.
4. The method according to claim 2 , wherein the etching is followed by sealing the etch material conduits.
5. The method according to claim 4 , wherein the optical system is included in a first wafer, wherein the sealing comprises bonding the first wafer to a second wafer.
6. The method according to claim 5 , further comprising thinning the second wafer and exposing second wafer vias formed within the second wafer, the second wafer vias are electrically coupled to first wafer vias of the first wafers that are electrically coupled to at least some electrodes of the actuation unit.
7. The method according to claim 5 , wherein the forming of the etch material conduits comprising coating a surface of the first wafer and the etch material conduits with a coating material, wherein the bonding is preceded by removing the coating material.
8. The method according to claim 7 , wherein the coating material is aluminum oxide.
9. The method according to claim 7 , further comprising thinning the first wafer.
10. The method according to claim 5 , wherein the bonding is preceded by filling at least a portion of the etch material conduits with a sealing material.
11. The method according to claim 1 , wherein the performing of the CMOS compliant operations comprises forming a first MSW segment conductive path to the first MSW segment and forming a second MSW segment conductive path to the second MSW segment.
12. The method according to claim 11 , wherein the performing of the CMOS compliant operations comprises forming a first substrate electrode conductive path to a first substrate electrode, and a second substrate electrode conductive path to a second substrate electrode.
13. The method according to claim 12 , wherein the performing of the CMOS compliant operations comprises forming a first distal electrode conductive path to a first distal electrode and forming a second distal electrode conductive path to a second distal electrode.
14. The method according to claim 13 , wherein the first MSW segment conductive path and the second MSW segment conductive path to the second MSW segment reach one facet of the first wafer and the first distal electrode conductive path, and the second distal electrode conductive path reach another facet of the first wafer.
15. The method according to claim 1 , wherein the performing of the CMOS compliant operations provides an array of switching cells, the array comprises the first switching cell.
16. The method according to claim 1 , wherein the silicon alloy layers comprise silicon germanium.
17. A method for manufacturing an optical system, the method comprises:
obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and
performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate,
wherein the first switching cell comprises: a first port, a second port, a third port, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment, and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide;
wherein the performing of the CMOS compliant operations comprises forming a Polysilicon layer or amorphous silicon layer for shielding the bus waveguides.
18. A non-transitory computer readable medium that stores instructions executable by a manufacturing system for:
obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and
performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate,
wherein the first switching cell comprises: a first port, a second port, a third port, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment, and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide;
wherein the performing of the CMOS compliant operations processes comprises etching the stack of layers by an etching process that exhibits a higher etching rate of the silicon alloy layers in comparison to an etching rate of the monocrystalline silicon layer.
19. The non-transitory computer readable medium according to claim 18 , wherein the performing of the CMOS compliant operations comprises forming a first MSW segment conductive path to the first MSW segment and forming a second MSW segment conductive path to the second MSW segment.
20. A non-transitory computer readable medium that stores instructions executable by a manufacturing system for:
obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and
performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate,
wherein the first switching cell comprises: a first port, a second port, a third port, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment, and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide;
wherein the performing of the CMOS compliant operations comprises forming a Polysilicon layer or amorphous silicon layer for shielding the bus waveguides.