Reset independent glitch filter
A glitch filtering circuit has a counting circuit configured to provide one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time; a flipflop clocked by a clock signal and configured to provide an output of the glitch filtering circuit; a threshold detect circuit configured to generate a select signal based on the one or more counter output signals; and a multiplexer configured to provide a multiplexed signal to an input of the flipflop, the multiplexed signal having a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to the output of the glitch filtering circuit.
1. A glitch filtering circuit, comprising:
a counting circuit configured to provide one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time;
a flipflop clocked by a clock signal and configured to provide an output of the glitch filtering circuit;
a threshold detect circuit configured to generate a select signal based on the one or more counter output signals; and
a multiplexer configured to provide a multiplexed signal to an input of the flipflop, the multiplexed signal having a signaling state that is selected in accordance with the select signal.
2. The glitch filtering circuit of claim 1 , wherein the counting circuit comprises:
a first counter configured to count cycles of the clock signal when the input signal is in the first signaling state; and
a second counter configured to count cycles of the clock signal when the input signal is in the second signaling state.
3. The glitch filtering circuit of claim 2 , wherein the one or more counter output signals comprise:
a first multibit signal indicative of an output of the first counter; and
a second multibit signal indicative of an output of the second counter,
wherein the threshold detect circuit is configured to generate the select signal by comparing the first multibit signal with a first threshold duration and the second multibit signal with a second threshold duration.
4. The glitch filtering circuit of claim 2 , wherein the one or more counter output signals comprise:
a first signal that is asserted when the input signal is in the first signaling state for a first threshold duration; and
a second signal that is asserted when the input signal is in the second signaling state for a second threshold duration,
wherein the threshold detect circuit is configured to generate the select signal based on a signaling state of the first signal and a signaling state of the second signal.
5. The glitch filtering circuit of claim 1 , wherein the counting circuit comprises:
a counter configured to count up when the input signal is in the first signaling state and to count down when the input signal is in the second signaling state.
6. The glitch filtering circuit of claim 5 , wherein the one or more counter output signals comprise:
a multibit signal indicative of a count value of the counter, wherein the threshold detect circuit is configured to generate the select signal by comparing the multibit signal with a threshold duration.
7. The glitch filtering circuit of claim 5 , wherein the one or more counter output signals comprise:
a first signal that is asserted when the input signal is in the first signaling state for a first threshold duration; and
a second signal that is asserted when the input signal is in the second signaling state for a second threshold duration,
wherein the threshold detect circuit is configured to generate the select signal based on a signaling state of the first signal and a signaling state of the second signal.
8. The glitch filtering circuit of claim 1 , wherein the multiplexed signal has a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to the output of the glitch filtering circuit.
9. The glitch filtering circuit of claim 1 , further comprising:
a logic circuit configured to provide state information related to operation of the glitch filtering circuit, wherein the state information includes information indicating that the output of the glitch filtering circuit is a stable representation of the signaling state of the input signal.
10. The glitch filtering circuit of claim 1 , wherein a reset input of the flipflop is disabled.
11. A method for filtering glitches from an input signal, comprising:
providing one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time;
generating a select signal based on state of the one or more counter output signals; and
providing a multiplexed signal to an input of a flipflop that is clocked by a clock signal, the multiplexed signal having a signaling state that is selected in accordance with the select signal.
12. The method of claim 11 , wherein providing the one or more counter output signals comprises:
providing a first count value by counting cycles of the clock signal when the input signal is in the first signaling state; and
providing a second count value by counting cycles of the clock signal when the input signal is in the second signaling state.
13. The method of claim 12 , wherein the select signal is generated based on comparisons of the first count value with a first threshold duration and comparisons of the second count value with a second threshold duration.
14. The method of claim 12 , wherein the select signal is generated using a first signal indicating that the first count value matches a first threshold duration, and using a second signal indicating that the second count value matches a second threshold duration.
15. The method of claim 11 , further comprising:
incrementing a counter when the input signal is in the first signaling state and decrementing the counter when the input signal is in the second signaling state.
16. The method of claim 15 , wherein the select signal is generated by comparing a multibit signal indicative of a count value of the counter with a threshold duration.
17. The method of claim 15 , wherein the select signal is generated by comparing a first signal with a second signal, wherein the first signal is asserted when the input signal is in the first signaling state for a first threshold duration and the second signal is asserted when the input signal is in the second signaling state for a second threshold duration.
18. The method of claim 11 , wherein the multiplexed signal has a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to an output of the flipflop.
19. The method of claim 11 , further comprising:
generating at least one signal representative of state information related to filtering glitches from the input signal, wherein the state information includes information indicating that an output of the flipflop is a stable representation of the signaling state of the input signal.
20. The method of claim 11 , wherein a reset input of the flipflop is disabled.
21. An apparatus, comprising:
means for providing one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time;
means for generating a select signal based on state of the one or more counter output signals; and
means for providing a multiplexed signal to an input of a flipflop that is clocked by a clock signal, the multiplexed signal having a signaling state that is selected in accordance with the select signal.
22. The apparatus of claim 21 , wherein the means for providing the one or more counter output signals comprises:
a first counter configured to count cycles of the clock signal when the input signal is in the first signaling state; and
a second counter configured to count cycles of the clock signal when the input signal is in the second signaling state.
23. The apparatus of claim 22 , wherein the one or more counter output signals comprise:
a first multibit signal indicative of count value of the first counter; and
a second multibit signal indicative of count value of the second counter,
wherein the threshold detect circuit is configured to generate the select signal by comparing the count value of the first counter to a first threshold duration and the count value of the second counter to a second threshold duration.
24. The apparatus of claim 22 , wherein the one or more counter output signals comprise:
a first signal that is asserted when the input signal is in the first signaling state for a first threshold duration; and
a second signal that is asserted when the input signal is in the second signaling state for a second threshold duration,
wherein the threshold detect circuit is configured to generate the select signal based on a signaling state of the first signal and a signaling state of the second signal.
25. The apparatus of claim 21 , wherein the means for providing the one or more counter output signals comprises:
a counter configured to count up when the input signal is in the first signaling state and to count down when the input signal is in the second signaling state.
26. The apparatus of claim 25 , wherein the one or more counter output signals comprise:
a multibit signal indicative of a count value of the counter, wherein the threshold detect circuit is configured to generate the select signal by comparing the count value of the counter with a threshold duration.
27. The apparatus of claim 25 , wherein the one or more counter output signals comprise:
a first signal that is asserted when the input signal is in the first signaling state for a first threshold duration; and
a second signal that is asserted when the input signal is in the second signaling state for a second threshold duration,
wherein the threshold detect circuit is configured to generate the select signal based on a signaling state of the first signal and a signaling state of the second signal.
28. The apparatus of claim 21 , wherein the multiplexed signal has a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to an output of the flipflop.
29. The apparatus of claim 21 , further comprising:
a logic circuit configured to provide state information related to operation of the apparatus, wherein the state information includes information indicating that an output of the flipflop is a stable representation of the signaling state of the input signal.
30. The apparatus of claim 21 , wherein a reset input of the flipflop is disabled.