Non-volatile storage of secure data in 6T SRAM cells using hot carrier injection
A processor has a Static Random Access Memory (SRAM) array with individual SRAM cells, each individual SRAM cell has six transistors including a first access transistor, a second access transistor, a first N-Channel Metal-Oxide Semiconductor (NMOS) transistor cross-coupled with a first P-Channel Metal-Oxide Semiconductor (PMOS) transistor forms a first inverter, and a second NMOS transistor cross-coupled with a second PMOS transistor forms a second inverter. The processor has a write driver. A global Hot Carrier Injection (HCI) driving circuit programs at least one individual SRAM cell by driving low the source of the first PMOS transistor and the source of the second PMOS transistor while driving high the source of the first NMOS transistor and the source of the second NMOS transistor while the write driver drives low a first bit line to the first access transistor, such that a large current flows through the first NMOS transistor from source to drain causing hot carriers to be injected into oxide of the first NMOS transistor and thereby alter the threshold voltage of the first NMOS transistor for stability over changing environmental conditions.
1. A processor, comprising:
a Static Random Access Memory (SRAM) array with individual SRAM cells, each individual SRAM cell comprising six transistors including a first access transistor, a second access transistor, a first N-Channel Metal-Oxide Semiconductor (NMOS) transistor cross coupled with a first P-Channel Metal-Oxide Semiconductor (PMOS) transistor to form a first inverter, a second NMOS transistor cross-coupled with a second PMOS transistor to form a second inverter;
a write driver; and
a global Hot Carrier Injection (HCI) driving circuit to program at least one individual SRAM cell by driving low the source of the first PMOS transistor and the source of the second PMOS transistor while driving high the source of the first NMOS transistor and the source of the second NMOS transistor while the write driver drives low a first bit line to the first access transistor, such that a large current flows through the first NMOS transistor from source to drain causing hot carriers to be injected into oxide of the first NMOS transistor and thereby alter the threshold voltage of the first NMOS transistor for stability over changing environmental conditions.
2. The processor of claim 1 further comprising a write buffer driving high a second bit line to the second access transistor causing a small current through the first PMOS transistor.
3. The processor of claim 2 wherein the second NMOS transistor and the second PMOS transistor remain off during the program.
4. The processor of claim 1 further comprising split word line drivers connected to the SRAM array.
5. The processor of claim 1 further comprising sense amplifiers connected to the SRAM array.
6. The processor of claim 1 further comprising a column logic connected to the SRAM array.
7. The processor of claim 1 further comprising an inter-column routing circuit connected to the SRAM array.