Scaled 2T DRAM
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.
1. A memory device comprising:
a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor,
wherein a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via, and wherein a channel region of the vertical transistor comprises indium-gallium-zinc-oxide (IGZO).
2. The memory device of claim 1 , wherein the IGZO in the channel region is horizontally surrounded by a metal gate via a layer of gate oxide.
3. The memory device of claim 2 , wherein the channel region of the vertical transistor has a vertical length that is equal to or larger than 10 nm.
4. The memory device of claim 1 , wherein the vertical transistor is a write-transistor and the nanosheet transistor is a read-transistor, and the write-transistor and the read-transistor form a dynamic random-access-memory (DRAM).
5. The memory device of claim 4 , wherein a top source/drain of the vertical transistor is connected to a write-bit-line, and a gate of the vertical transistor is connected to a write-word-line.
6. The memory device of claim 1 , wherein the nanosheet transistor has a dimension measured from a first source/drain region to a second source/drain region, and wherein a channel region of the vertical transistor is horizontally smaller than the dimension of the nanosheet transistor.
7. The memory device of claim 1 , wherein the nanosheet transistor has three or more nanosheets.
8. A semiconductor structure comprising:
a dynamic random-access-memory (DRAM), the DRAM comprising:
a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor,
wherein a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via; and
a frontside interconnect underneath the nanosheet transistor and a backside interconnect above a top source/drain of the vertical transistor.
9. The semiconductor structure of claim 8 , wherein a channel region of the vertical transistor comprises indium-gallium-zinc-oxide (IGZO).
10. The semiconductor structure of claim 9 , wherein the IGZO in the channel region is horizontally surrounded by a metal gate via a layer of gate oxide.
11. The semiconductor structure of claim 9 , wherein the vertical transistor is a write-transistor and the nanosheet transistor is a read-transistor of the DRAM.
12. The semiconductor structure of claim 11 , wherein the top source/drain of the vertical transistor is connected to a write-bit-line and a gate of the vertical transistor is connected to a write-word-line, both the write-bit-line and the write-word-line being in the backside interconnect.
13. The semiconductor structure of claim 11 , wherein a first source/drain of the nanosheet transistor is connected to a read-bit-line in the frontside interconnect, and a second source/drain of the nanosheet transistor is grounded.
14. A method of forming a semiconductor structure comprising:
forming a nanosheet transistor;
flipping the nanosheet transistor upside-down; and
forming a vertical transistor on top of the nanosheet transistor,
wherein a bottom source/drain of the vertical transistor is connected to a gate of the nanosheet transistor.
15. The method of claim 14 , wherein forming the vertical transistor comprises:
removing a substrate upon which the nanosheet transistor is formed until an etch-stop layer is exposed;
depositing a dielectric layer on top of the etch-stop layer;
creating an opening in the dielectric layer and the etch-stop layer to expose the gate of the nanosheet transistor; and
forming a conductive via in the opening to contact the gate of the nanosheet transistor.
16. The method of claim 15 , wherein forming the vertical transistor further comprises:
forming a stack of layers on top of the dielectric layer and the conductive via; and
patterning the stack of layers into the bottom source/drain, a channel region, and a top source/drain of the vertical transistor.
17. The method of claim 16 , wherein forming the vertical transistor further comprises:
forming a gate dielectric horizontally surrounding the channel region; and
forming a metal gate horizontally surrounding the channel region and the gate dielectric,
wherein the channel region comprises indium-gallium-zinc-oxide (IGZO).
18. The method of claim 16 , wherein patterning the stack of layers comprises forming the bottom source/drain, the channel region, and the top source/drain to have a horizontal dimension that is smaller than a dimension of the nanosheet transistor, the dimension of the nanosheet transistor being measured from a first source/drain region to a second source/drain region of the nanosheet transistor.