Clock frequency adjusting circuit and method for adjusting clock frequency
An adjusting circuit includes: a detection circuit outputting a detection signal indicative of whether a noise occurs in electric power inputted into an integrated circuit operating in synchronization with a clock signal; and a controlling circuit outputting to the integrated circuit a first clock signal having a first frequency, or a second clock signal having a second frequency lower than the first frequency when the detection signal indicates the noise occurs. The detection circuit includes a first circuit outputting a first delayed clock signal obtained by delaying the first clock signal according to an operation voltage of the integrated circuit, a second circuit outputting a second delayed clock signal obtained by delaying the first clock signal according to a threshold voltage lower than the operation voltage, and an output circuit outputting the detection signal based on a result of comparing phases of the first and second delayed clock signals.
1. A clock frequency adjusting circuit comprising:
a detection circuit that outputs a detection signal indicative of whether a noise occurs in electric power inputted into an integrated circuit operating in synchronization with a clock signal; and
a clock frequency controlling circuit that outputs a first clock signal having a first clock frequency to the integrated circuit, and outputs, when the detection signal inputted from the detection circuit indicates occurrence of the noise, a second clock signal having a second clock frequency lower than the first clock frequency to the integrated circuit in place of the first clock signal,
the detection circuit comprising
a first delay circuit that outputs a first delayed clock signal obtained by delaying the first clock signal according to an operation voltage of the integrated circuit,
a second delay circuit that outputs a second delayed clock signal obtained by delaying the first clock signal according to a threshold voltage lower than the operation voltage, and
a detection signal output circuit that outputs the detection signal based on a result of comparing a phase of the first delayed clock signal inputted from the first delay circuit and a phase of the second delayed clock signal inputted from the second delay circuit,
the detection signal output circuit comprising
a comparison circuit that outputs the result of the comparing based on whether a rising timing of the first delayed clock signal is earlier than a rising timing of the second delayed clock signal, and
an output circuit that outputs the result of the comparing at a timing synchronized with the first clock signal.
2. The clock frequency adjusting circuit according to claim 1 , further comprising an adjustment circuit that adjusts respective amounts of delays in the first delay circuit and the second delay circuit such that the delays by which the first clock signal are delayed in the first delay circuit and the second delay circuit according to the threshold voltage come to be within a clock cycle of the first clock frequency.
3. The clock frequency adjusting circuit according to claim 2 , wherein the adjustment circuit adjusts the respective amounts of the delays in the first delay circuit and the second delay circuit such that the delay by which the first clock signal is delayed according to the threshold voltage is maximized in the clock cycle of the first clock frequency.
4. The clock frequency adjusting circuit according to claim 2 , wherein the adjustment circuit
stores, in a storing region, the amounts of delays of the first delay circuit and the second delay circuit for each combination of the threshold voltage and the first clock frequency, and
reads, from the storing region, amounts of delays associated with a combination of a threshold voltage corresponding to an operation voltage of the integrated circuit and the first clock frequency in response to a change at least one of the operation voltage of the integrated circuit and the first clock frequency and sets the read amounts of the delays in the first delay circuit and the second delay circuit.
5. A method of adjusting a clock frequency in a clock frequency adjusting circuit comprising a detection circuit and a clock frequency controlling circuit, the method comprising:
at the detection circuit
outputting, from a first delay circuit, a first delayed clock signal obtained by delaying a first clock signal according to an operation voltage of an integrated circuit operating in synchronization with a clock signal, the first clock signal being inputted from the clock frequency controlling circuit and having a first clock frequency,
outputting, from a second delay circuit, a second delayed clock signal obtained by delaying the first clock signal according to a threshold voltage lower than the operation voltage,
outputting, based on a result of comparing a phase of the first delayed clock signal inputted from the first delay circuit and a phase of the second delayed clock signal inputted from the second delay circuit, a detection signal indicative of whether a noise occurs in electric power inputted into the integrated circuit from a detection signal output circuit,
at the clock frequency controlling circuit
outputting the first clock signal to the integrated circuit,
outputting, when the detection signal inputted from the detection circuit indicates occurrence of the noise, a second clock signal having a second clock frequency lower than the first clock frequency to the integrated circuit in place of the first clock signal,
at the detection signal output circuit
outputting the result of the comparing based on whether a rising timing of the first delayed clock signal is earlier than a rising timing of the second delayed clock signal from a comparison circuit, and
outputting the result of the comparing from an output circuit at a timing synchronized with the first clock signal.
6. The method according to claim 5 , further comprising
at an adjustment circuit included in the clock frequency adjusting circuit
adjusting respective amounts of delays in the first delay circuit and the second delay circuit such that the delays by which the first clock signal are delayed in the first delay circuit and the second delay circuit according to the threshold voltage come to be within a clock cycle of the first clock frequency.
7. The method according to claim 6 , further comprising
at the adjustment circuit
adjusting the respective amounts of the delays in the first delay circuit and the second delay circuit such that the delay by which the first clock signal is delayed according to the threshold voltage is maximized in the clock cycle of the first clock frequency.
8. The method according to claim 6 , further comprising:
at the adjustment circuit
storing, in a storing region, the amounts of delays of the first delay circuit and the second delay circuit for each combination of the threshold voltage and the first clock frequency, and
reading, from the storing region, amounts of delays associated with a combination of a threshold voltage corresponding to an operation voltage of the integrated circuit and the first clock frequency in response to a change at least one of the operation voltage of the integrated circuit and the first clock frequency and setting the read amounts of the delays in the first delay circuit and the second delay circuit.