System, apparatus and method for dynamically configuring one or more hardware resources of a processor
In one embodiment, a processor includes: at least one configuration register to store configuration information for a hardware resource including a control circuit to configure the hardware resource based at least in part on the configuration information; a performance monitor to maintain performance information during execution of an application on the processor; and a controller coupled to the at least one configuration register. The controller may dynamically provide the configuration information to the at least one configuration register based at least in part on the performance information, and the control circuit is to adjust a performance tuning of the hardware resource according to the configuration information. Other embodiments are described and claimed.
1. At least one computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
executing, by a processor, an application having a plurality of phases, the executing comprising iteratively executing the application with a different set of configuration values for at least one hardware resource of the processor during each iterative execution of the application, the executing further comprising iteratively executing a first phase of the application with each of the different sets of configuration values;
maintaining performance monitoring information obtained for the plurality of phases for each iterative execution of the application;
identifying an optimal set of configuration values, the optimal set of configuration values with respect to an optimization cost function, from the different sets of configuration values for each of the plurality of phases based at least in part on the performance monitoring information, the identifying comprising identifying an optimal set of configuration values for the first phase based at least in part on corresponding performance monitoring information indicating at least one of a highest performance level and a lowest power consumption level associated with the optimal set of configuration values for the first phase; and
storing the optimal set of configuration values for each of the plurality of phases in a non-volatile storage.
2. The at least one computer readable storage medium of claim 1 , wherein the method further comprises forming a machine learning model comprising a plurality of entries, each of the plurality of entries comprising an optimal set of configuration values for one of the plurality of phases and corresponding performance monitoring information associated with the optimal set of configuration values for the one of the plurality of phases.
3. The at least one computer readable storage medium of claim 2 , wherein the method further comprises providing the machine learning model to a plurality of processors to enable the plurality of processors to dynamically reconfigure configuration settings for one or more hardware resources of the plurality of processors using the machine learning model.
4. The at least one computer readable storage medium of claim 3 , wherein the method further comprises dynamically updating the machine learning model and providing the updated machine learning model to one or more of the plurality of processors as an in-field patch update.
5. The at least one computer readable storage medium of claim 1 , wherein the method further comprises identifying the plurality of phases based on a predetermined number of instructions of the application.
6. The at least one computer readable storage medium of claim 1 , wherein the method further comprises obtaining an application checkpoint at a conclusion of the first phase of the application, the application checkpoint obtained using the optimal set of configuration values for the first phase.
7. The at least one computer readable storage medium of claim 6 , wherein the method further comprises using the application checkpoint to begin iteratively executing a second phase of the application with the different sets of configuration values for the at least one hardware resource, the second phase of the application following the first phase of the application.
8. A system comprising:
at least one processor to execute instructions; and
at least one computer readable storage medium coupled to the at least one processor, the at least one computer readable storage medium comprising instructions which, when executed by the at least one processor, cause the at least one processor to:
iteratively execute an application having a plurality of phases, each iterative execution of the application using a different set of configuration values for at least one hardware resource of a system on chip (SoC);
maintain performance monitoring information for the plurality of phases for each iterative execution of the application;
identify, based on an optimization cost function, an optimal set of configuration values from the different sets of configuration values for a respective phase of the plurality of phases based at least in part on the performance monitoring information, the optimal set of configuration values associated with at least one of a highest performance and a lowest power consumption for the respective phase indicated by the performance monitoring information;
generate a machine learning model comprising the optimal set of configuration values for each of the plurality of phases, each of the optimal set of configuration values associated with one or more performance metric values; and
provide the machine learning model for storage in a non-volatile memory of a plurality of SoCs to cause the plurality of SoCs to dynamically configure the one or more hardware resources of the plurality of SoCs during execution of the application.
9. The system of claim 8 , wherein the at least one computer readable storage medium further comprises instructions which, when executed by the at least one processor, cause the at least one processor to dynamically update the machine learning model and provide the updated machine learning model to one or more of the plurality of SoCs as an in-field patch update.
10. A method comprising:
executing, by a processor, an application having a plurality of phases identified based on a predetermined number of instructions of the application, the executing comprising iteratively executing the application with a different set of configuration values for at least one hardware resource of the processor during each iterative execution of the application;
maintaining performance monitoring information obtained for the plurality of phases for each iterative execution of the application;
identifying, based at least in part on instructions per cycle, an optimal set of configuration values from the different sets of configuration values for a respective phase of the plurality of phases based at least in part on the performance monitoring information, the optimal set of configuration values associated with at least one of a highest performance and a lowest power consumption for the respective phase indicated by the associated performance monitoring information; and
storing the optimal set of configuration values for each of the plurality of phases in a non-volatile storage.
11. The method of claim 10 , further comprising forming a machine learning model comprising a plurality of entries, each of the plurality of entries comprising an optimal set of configuration values for one of the plurality of phases and corresponding performance monitoring information associated with the optimal set of configuration values for the one of the plurality of phases.
12. The method of claim 11 , further comprising providing the machine learning model to a plurality of processors to enable the plurality of processors to dynamically reconfigure configuration settings for one or more hardware resources of the plurality of processors using the machine learning model.
13. The method of claim 12 , further comprising dynamically updating the machine learning model and providing the updated machine learning model to one or more of the plurality of processors as an in-field patch update.