Granted Patent B2

US 12,367,249 · App. 17/505,568 · Granted Jul 22, 2025

Inventors: Anthony Sarah (San Diego, CA); Daniel Cummings (Austin, TX); Juan Pablo Munoz (Folsom, CA); Tristan Webb (San Diego, CA)

Assignee: Intel Corporation

G06F16/953G06N5/027

Abstract

Claims (49)

1. An apparatus for identifying machine learning (ML) architectures, the apparatus comprising:

interface circuitry to obtain an ML configuration, the ML configuration including a current set of input search parameters;

machine-readable instructions; and

at least one processor circuit to be programmed based on the machine-readable instructions to:

identify a set of previous ML architectures based on previous searches using respective previous sets of input search parameters, the previous sets of input search parameters different from the current set of input search parameters but having at least one of an ML task, an ML domain or hardware platform information in common with the current set of search parameters;

initialize a set of candidate ML architectures to include the set of previous ML architectures;

search the set of candidate ML architectures based on the current set of input search parameters;

determine, based on the search, an output set of ML architectures from the set of candidate ML architectures, the output set of ML architectures to satisfy one or more of the current set of search parameters; and

evaluate performance of ones of the ML architectures in the output set of ML architectures.

2. The apparatus of claim 1 , wherein the ML configuration includes a super-network, and one or more of the at least one processor circuit is to generate sub-networks of the super-network to include in the set of candidate ML architectures, the sub-networks to have fewer ML parameters than the super-network.

3. The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to search the set of candidate ML architectures based on one or more constraints between two or more ML parameters of the candidate ML architectures in the initialized set of candidate ML architectures.

4. The apparatus of claim 1 , wherein the search is based on an algorithm, and one or more of the at least one processor circuit is to select the algorithm from a plurality of algorithms based on at least one of hardware platform information or a performance metric included in the ML configuration.

5. The apparatus of claim 4 , wherein the algorithms include one or more of grid search, random search, Bayesian optimization, an evolutionary algorithm, a tree-structured Parzen estimator, or a user-defined optimization algorithm.

6. The apparatus of claim 5 , wherein the algorithms include the evolutionary algorithm, and the evolutionary algorithm is one of Strength Pareto Evolutionary Algorithm 2 (SPEA-2) or Nondominated Sorting Genetic Algorithm-II.

7. The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to determine the set of optimal ML architectures to be a set of Pareto optimal solutions.

8. The apparatus of claim 7 , wherein one or more of the at least one processor circuit is to:

for successive iterations until convergence is reached:

rank ones of the candidate ML architectures in the set of candidate ML architectures;

perform crowding distance sorting to select individual candidate ML architectures from the ranked set of candidate ML architectures; and

carry the selected individual candidate ML architectures into a next optimization iteration.

9. The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to:

measure one or more performance metrics based on operation of ones of the ML architectures in the output set of ML architectures using a test dataset.

10. The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to:

predict one or more performance metrics of ones of the ML architectures in the output set of ML architectures using one or more proxy functions.

11. The apparatus of claim 10 , wherein the one or more proxy functions include one or more of associative arrays, mapping functions, dictionaries, hash tables, look-up tables (LUTs), linked lists, ML classifiers, parameter counting, computational throughput metrics, Jacobian covariance functions, saliency pruning functions, channel pruning functions, heuristic functions, or hyper-heuristic functions.

12. The apparatus of claim 1 , wherein the ML configuration includes an identifier of a hardware platform on which a selected one of the output set of ML architectures is to be deployed.

13. The apparatus of claim 1 , wherein the ML configuration includes data of one or more hardware components of a hardware platform.

14. One or more non-transitory computer readable media (NTCRM) comprising instructions to cause at least one processor circuit to at least:

access a machine learning (ML) configuration from a client device;

determine a set of candidate ML architectures based on sub-networks included in a super-network indicated by the ML configuration;

determine, based on the set of candidate ML architectures, an output set of ML architectures that satisfy at least one of an ML parameter or hardware platform information (HPI) included in the ML configuration;

determine performance metrics for the set of optimal ML architectures; and

cause presentation of information corresponding to the output set of ML architectures and the determined performance metrics at the client device.

15. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

obtain a selection of one of the MP architectures from among the output set of ML architectures; and

cause the selected one of the ML architectures to be sent to the client device.

16. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to determine the output set of ML architectures to be a Pareto frontier of a multi-objective optimization problem, and the information includes a graphical representation of the Pareto frontier.

17. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

determine the set of candidate ML architectures to include first ones of the sub-networks that were previously found to satisfy the at least one of the ML parameter or the HPI; or

determine the set of candidate ML architectures to include second ones of the sub-networks that satisfy one or more heuristics derived from at least one previously generated output ML architecture, the one or more heuristics to indicate a relationship between individual ML parameters of the at least one previously generated output ML architecture.

18. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

search the set of candidate ML architectures based on one or more constraints between two or more ML parameters of the candidate ML architectures in the set of candidate ML architectures.

19. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

operate one or more algorithms to determine the output set of ML architectures based on the set of candidate ML architectures, the one or more optimization algorithms including one or more of grid search, random search, Bayesian optimization, a genetic algorithm, a tree-structured Parzen estimator, Strength Pareto Evolutionary Algorithm 2 (SPEA-2), Nondominated Sorting Genetic Algorithm-II, or a user-defined optimization algorithm.

20. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

measure the performance metrics based on operation of ones of the ML architectures in the output set of ML architectures using a test dataset.

21. The one or more NTCRM of claim 14 , wherein the instructions are to cause one or more of the at least one processor circuit to:

predict one or more of the performance metrics based on one or more proxy functions, the one or more proxy functions including one or more of associative arrays, mapping functions, dictionaries, hash tables, look-up tables (LUTs), linked lists, ML classifiers, parameter counting, computational throughput metrics, Jacobian covariance functions, saliency pruning functions, channel pruning functions, heuristic functions, or hyper-heuristic functions.

22. The one or more NTCRM of claim 14 , wherein one or more of the at least one processor circuit is to determine the output set of ML architectures to satisfy at least the HPI, and the HPI includes technical data of a hardware platform or technical data of one or more hardware components of the hardware platform.

Assignments (1)

Continuity (1)

References Cited (180)

Cited By (1)

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