Granted Patent B2

US 12,373,515 · App. 18/633,703 · Granted Jul 29, 2025

Inventors: Arthur John Redfern (Plano, TX); Timothy David Anderson (University Park, TX); Kai Chirca (Dallas, TX); Chenchi Luo (Plano, TX); Zhenhua Yu (Santa Clara, CA)

Assignee: TEXAS INSTRUMENTS INCORPORATED

G06F17/16G06F17/141G06N3/045G06N3/063

Abstract

Claims (68)

1. A device comprising:

a memory;

a processor coupled to the memory; and

a matrix multiplication accelerator (MMA) coupled to the processor and including a multiplier matrix buffer and a multiplicand matrix buffer,

wherein the device is operable to:

receive a data vector including a filter of a length greater than a width of the multiplicand matrix buffer;

decompose the filter into a plurality of smaller filters, wherein sizes of the smaller filters are less than the width of the multiplicand matrix buffer;

format the data vector based on a computational primitive; and

configure, based on the computational primitive, the MMA to format the data vector.

2. The device of claim 1 , wherein the processor is configurable to decompose the filter into the plurality of smaller filters.

3. The device of claim 1 ,

wherein the data vector comprises a row of a matrix, and

wherein the MMA is configurable to execute the computational primitive by at least copying the data vector to a column in the multiplicand matrix buffer.

4. The device of claim 1 , wherein the device is operable to configure the MMA to offset load data in the multiplicand matrix buffer.

5. The device of claim 1 ,

wherein the MMA is configurable to execute the computational primitive to generate an output, and

wherein the processor is configurable to add zero padding to the output of the MMA.

6. The device of claim 1 ,

wherein the MMA is configurable to execute the computational primitive to generate an output, and

wherein the processor is configurable to perform seam removal on the output of the MMA.

7. The device of claim 1 ,

wherein the MMA is configurable to execute the computational primitive to generate an output, and

wherein the processor is configurable to perform column subsampling on the output of the MMA according to a specified stride.

8. The device of claim 1 , further comprising a streaming engine configurable to tile data of a plurality of feature maps into a filtering matrix.

9. The device of claim 8 ,

wherein the MMA is configurable to execute the computational primitive to generate an output, and

wherein a size of a tile of data is selected such that no seam is present in the output of the MMA.

10. The device of claim 8 ,

wherein the MMA is configurable to execute the computational primitive to generate an output, and

wherein a size of a tile of data is selected such that a seam is always in a same location in the output of the MMA.

11. The device of claim 1 ,

wherein the data vector includes complex numbers,

wherein a real part and an imaginary part of the complex numbers are stored interleaved in the memory, and

wherein the processor is configurable to split each complex number into the real part and the imaginary part for loading into the MMA.

12. The device of claim 1 ,

wherein the computational primitive is a fast Fourier transform (FFT), and

wherein the MMA is configurable to execute the computational primitive by at least:

loading a discrete Fourier transform (DFT) matrix in the multiplier matrix buffer;

loading a data matrix in the multiplicand matrix buffer to perform the FFT on columns of the data matrix; and

loading the data matrix in the multiplier matrix buffer and the DFT matrix into the multiplicand matrix buffer to perform the FFT on rows of the data matrix.

13. The device of claim 1 , wherein the sizes of the smaller filters are selected as a tradeoff between maximizing a throughput of the MMA and minimizing a total number of smaller filters.

14. A method for performing a computational primitive in a device comprising a processor and a matrix multiplication accelerator (MMA), the method comprising:

receiving a data vector including a filter of a length greater than a width of a multiplicand matrix buffer in the MMA;

decomposing the filter into a plurality of smaller filters, wherein sizes of the smaller filters are less than the width of the multiplicand matrix buffer;

formatting the data vector based on the computational primitive; and

configuring, based on the computational primitive, the MMA to format the data vector.

15. The method of claim 14 ,

wherein the data vector comprises a row of a matrix, and

wherein the method further comprises executing the computational primitive by at least copying the data vector to a column in the multiplicand matrix buffer.

16. The method of claim 14 , further comprising:

executing the computational primitive to generate an output; and

adding zero padding to the output of the MMA.

17. The method of claim 14 , further comprising:

executing the computational primitive to generate an output; and

performing seam removal on the output of the MMA.

18. The method of claim 14 , further comprising:

executing the computational primitive to generate an output; and

performing column subsampling on the output of the MMA according to a specified stride.

19. The method of claim 14 , further comprising:

executing the computational primitive to generate an output;

tiling data of a plurality of feature maps into a filtering matrix; and

selecting a size of a tile of data such that no seam is present in the output of the MMA.

20. The method of claim 14 ,

wherein the computational primitive is a fast Fourier transform (FFT), and

wherein the method further comprises executing the computational primitive by at least:

loading a discrete Fourier transform (DFT) matrix in the multiplier matrix buffer;

loading a data matrix in the multiplicand matrix buffer to perform the FFT on columns of the data matrix; and

loading the data matrix in the multiplier matrix buffer and the DFT matrix into the multiplicand matrix buffer to perform the FFT on rows of the data matrix.

Continuity (4)

References Cited (49)