Serial bus redriver with trailing edge boost circuit
A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
1. A serial bus re-driver circuit, comprising:
a serial bus terminal;
an edge detector circuit comprising:
an input terminal coupled to the serial bus terminal; and
an output terminal; and
a booster circuit coupled to the edge detector circuit, and comprising:
a leading edge boost pulse generation circuit comprising:
an input terminal coupled to the output terminal of the edge detector circuit; and
a leading edge boost pulse output terminal;
a trailing edge boost pulse generation circuit coupled to the leading edge boost generation circuit, and comprising:
a pulse shortening circuit coupled to the leading edge boost pulse output terminal;
a pulse gating circuit coupled to the pulse shortening circuit; and
a drive transistor coupled to the pulse gating circuit and the serial bus terminal;
wherein the pulse shortening circuit comprises:
a first delay cell comprising:
an input terminal coupled to the leading edge boost pulse output terminal; and
an output terminal;
a second delay cell comprising:
an input terminal coupled to the output terminal of the first delay cell; and
an output terminal;
a conjunctive logic circuit comprising:
a first input terminal coupled to the output terminal of the first delay cell;
a second input terminal coupled to the output terminal of the second delay cell; and
an output terminal coupled to the drive transistor;
wherein:
the pulse gating circuit is a first pulse gating circuit;
the drive transistor is a first drive transistor; and
the serial bus re-driver circuit further comprises:
a second drive transistor;
a third delay cell comprising:
an input terminal coupled to the output terminal of the conjunctive logic circuit; and
an output terminal;
a second pulse gating circuit comprising:
a first logic gate comprising:
a first input terminal coupled to the output terminal of the edge detector circuit;
a second input terminal coupled to the output terminal of the third delay cell; and
an output terminal; and
a second logic gate comprising:
a first input terminal coupled to the output terminal of the first logic gate;
a second input terminal coupled to the leading edge boost pulse output terminal; and
an output terminal coupled to the second drive transistor.
2. The serial bus re-driver circuit of claim 1 , wherein the pulse shortening circuit comprises:
a third delay cell comprising:
an input terminal coupled to the output terminal of the second delay cell; and
an output terminal coupled to a third input terminal of the conjunctive logic circuit.
3. The serial bus re-driver circuit of claim 1 , further comprising:
a delay calibration circuit coupled to the first delay cell and the second delay cell, and comprising:
a third delay cell comprising:
a signal input terminal coupled to the leading edge boost pulse output terminal;
a calibration input terminal; and
an output terminal;
a first flip-flop comprising:
a data input terminal coupled to the leading edge boost pulse output terminal;
a clock input terminal coupled to the output terminal of the third delay cell; and
an output terminal;
a second flip-flop comprising:
a data input terminal coupled to the output terminal of the third delay cell;
a clock input terminal coupled to the leading edge boost pulse output terminal; and
an output terminal;
a counter comprising:
a first input terminal coupled to the output of the first flip-flop;
a second input terminal coupled to the output of the second flip-flop;
a clock input terminal coupled to the output terminal of the edge detector circuit; and
an output terminal coupled to the calibration input terminal of the third delay cell.
4. The serial bus re-driver circuit of claim 1 , wherein:
the first delay cell comprises a calibration input terminal;
the second delay cell comprises a calibration input terminal; and
the output terminal of the counter is coupled to the calibration input terminal of the first delay cell and the calibration input terminal of the second delay cell.