Semiconductor package
A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.
1. A semiconductor package, comprising:
a package substrate;
a first semiconductor chip mounted on the package substrate;
an interposer including supporters on a bottom surface of the interposer and a first vent hole centrally formed in the interposer, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals;
second semiconductor chips mounted on the interposer; and
a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chips,
wherein the first vent hole is placed between the second semiconductor chips, and
wherein the molding layer fills the first vent hole, a space between the first semiconductor chip and the interposer, and a space between the second semiconductor chips and the interposer.
2. The semiconductor package of claim 1 , wherein the package substrate includes a second vent hole centrally formed in the package substrate, and
wherein the molding layer further fills the second vent hole.
3. The semiconductor package of claim 2 , wherein the second vent hole is below the first semiconductor chip, and
wherein the molding layer extends through the second vent hole to cover at least a portion of a bottom surface of the package substrate.
4. The semiconductor package of claim 3 , further comprising a plurality of external terminals on the bottom surface of the package substrate,
wherein a distance between the bottom surface of the package substrate and a bottom surface of the molding layer is less than a distance between the bottom surface of the package substrate and bottom surfaces of the external terminals.
5. The semiconductor package of claim 1 , wherein the interposer includes a central region disposed above the first semiconductor chip and an overhang region disposed to one side of the central region,
wherein the first vent hole and the supporters are disposed in the central region, and
wherein the connection terminals are disposed in the overhang region.
6. The semiconductor package of claim 1 , wherein the interposer includes an elliptically-shaped central region disposed below the second semiconductor chips and a peripheral region surrounding the central region, and
wherein the supporters are arranged in one of a grid pattern and a honeycomb pattern.
7. The semiconductor package of claim 1 , wherein each one of the supporters has a height of about 20 μm to about 300 μm.
8. The semiconductor package of claim 1 , wherein, when viewed in a plan view, the first vent hole is between the supporters.
9. The semiconductor package of claim 1 , further comprising a third semiconductor chip mounted on the package substrate,
wherein the third semiconductor chip is horizontally spaced apart from the first semiconductor chip between the package substrate and the interposer,
wherein the package substrate has a third vent hole between the first semiconductor chip and the third semiconductor chip,
wherein the molding layer further fills a space between the third semiconductor chip and the interposer, and
wherein the molding layer extends through the third vent hole to cover at least a portion of a bottom surface of the package substrate.
10. A semiconductor package, comprising:
a package substrate including a first vent hole centrally formed in the package substrate;
a first lower semiconductor chip mounted on the package substrate;
a second lower semiconductor chip mounted on the package substrate;
an interposer including first supporters on a bottom surface of the interposer contacting a top surface of the first lower semiconductor chip, and second supporters on the bottom surface of the interposer contacting a top surface of the second lower semiconductor chip, wherein the interposer is electrically connected to the package substrate through connection terminals;
an upper semiconductor chip mounted on the interposer; and
a molding layer disposed on the package substrate to cover a combination of first lower semiconductor chip, the second lower semiconductor chip, the interposer, and the upper semiconductor chip,
wherein the first vent hole is placed between the first lower semiconductor chip and the second lower semiconductor chip, and
wherein the molding layer fills a space inside of the first vent hole, a space between the first lower semiconductor chip and the second lower semiconductor chip and the interposer, and a space between the upper semiconductor chip and the interposer.
11. The semiconductor package of claim 10 , wherein the package substrate further includes second vent holes laterally spaced apart from the first vent hole, and
wherein the molding layer further fills the first vent hole and the second vent holes.
12. The semiconductor package of claim 11 , wherein the second vent holes are below the first lower semiconductor chip and the second lower semiconductor chip.
13. The semiconductor package of claim 11 , wherein the molding layer extends through the first vent hole and the second vent holes to cover at least a portion of a bottom surface of the package substrate.
14. The semiconductor package of claim 13 , further comprising a plurality of external terminals on the bottom surface of the package substrate,
wherein a distance between the bottom surface of the package substrate and a bottom surface of the molding layer is less than a distance between the bottom surface of the package substrate and bottom surfaces of the external terminals.
15. The semiconductor package of claim 11 , wherein the interposer includes a third vent hole centrally formed in the interposer, and
wherein the molding layer further fills the third vent hole.
16. The semiconductor package of claim 15 , wherein the third vent hole is disposed between the first lower semiconductor chip and the second lower semiconductor chip, and
wherein the first supporters are disposed in the first lower semiconductor chip and on the second lower semiconductor chip.
17. The semiconductor package of claim 15 , wherein, when viewed in a plan view, the third vent hole is between the first supporters.
18. The semiconductor package of claim 15 , wherein the upper semiconductor chip includes a plurality of upper semiconductor chips,
wherein the upper semiconductor chips are horizontally spaced apart from each other, and
wherein the third vent hole is disposed between the upper semiconductor chips.
19. The semiconductor package of claim 10 , wherein each one of the first and second supporters has a height of about 20 μm to about 300 μm.
20. A semiconductor package, comprising:
a package substrate including a first vent hole centrally formed in the package substrate;
lower semiconductor chips mounted on the package substrate and horizontally spaced apart from each other;
an interposer mounted on the package substrate, including a second vent hole centrally-formed in the interposer;
upper semiconductor chips mounted on the interposer and horizontally spaced apart from each other; and
a molding layer disposed on the package substrate to cover a combination of lower semiconductor chips, the interposer, and the upper semiconductor chips,
wherein the first vent hole is placed between the lower semiconductor chips,
wherein the second vent hole is placed between the upper semiconductor chips,
wherein the molding layer includes a first part filling the first vent hole and extending to cover at least a portion of a bottom surface of the package substrate, a second part filling a space between the lower semiconductor chips and the interposer, and a third part filling a space between the upper semiconductor chips and the interposer, and
wherein the interposer is electrically connected to the package substrate through connection terminals disposed to one side of the lower semiconductor chips.