Bipolar selector with independently tunable threshold voltages
Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
1. An integrated chip comprising a memory cell, wherein the memory cell comprises:
a data-storage element; and
a bipolar selector electrically coupled in series with the data-storage element and comprising a first unipolar selector and a second unipolar selector, wherein the first and second unipolar selectors are electrically coupled in parallel with opposite orientations;
wherein the first unipolar selector has a different threshold voltage than a threshold voltage of the second unipolar selector and further has a different ON resistance than an ON resistance of the second unipolar selector.
2. The integrated chip according to claim 1 , further comprising:
a first array comprising a first plurality of memory cells in a plurality of rows and a plurality of columns;
a second array overlying the first array and comprising a second plurality of memory cells in the plurality of rows and the plurality of columns; and
a plurality of first conductive lines at a common elevation between the first and second arrays, wherein the first conductive lines extend correspondingly along the columns and electrically couple with memory cells of the first and second arrays in the corresponding columns;
wherein the first or second array comprises the memory cell.
3. The integrated chip according to claim 1 , wherein the first unipolar selector has a lesser threshold voltage than the threshold voltage of the second unipolar selector and further has a lesser ON resistance than the ON resistance of the second unipolar selector.
4. The integrated chip according to claim 3 , wherein the memory cell is configured so the first unipolar selector is ON during read operations and the second unipolar selector is OFF during read operations.
5. The integrated chip according to claim 1 , wherein the first and second unipolar selectors comprise individual insulators having different thicknesses.
6. The integrated chip according to claim 1 , wherein the first unipolar selector has a lesser length than the second unipolar selector and further has a greater width than the second unipolar selector.
7. The integrated chip according to claim 1 , wherein the first unipolar selector has a current-voltage curve in which a voltage increases with current until a first current value is reached, in which the voltage decreases as current increases above the first current value until a second current value is reached, and in which the voltage increases with current above the second current value.
8. An integrated chip, comprising:
a first array comprising a first plurality of memory cells in a plurality of rows and a plurality of columns;
a second array overlying the first array and comprising a second plurality of memory cells in the plurality of rows and the plurality of columns; and
a plurality of first conductive lines at a common elevation between the first and second arrays, wherein the first conductive lines extend correspondingly along the columns and electrically couple with memory cells of the first and second arrays in the corresponding columns;
wherein a memory cell of the first or second array comprises a data-storage element and a bipolar selector that are electrically coupled in series, and wherein the bipolar selector comprises a first unipolar selector and a second unipolar selector that are electrically coupled in parallel with opposite orientations.
9. The integrated chip according to claim 8 , wherein the first unipolar selector has a different threshold voltage than a threshold voltage of the second unipolar selector and further has a different ON resistance than an ON resistance of the second unipolar selector.
10. The integrated chip according to claim 8 , further comprising:
a plurality of second conductive lines and a plurality of third conductive lines respectively underlying the first array and overlying the second array, wherein the second conductive lines extend correspondingly along the rows and electrically couple with memory cells of the first array in the corresponding rows, and wherein the third conductive lines extend correspondingly along the rows and electrically couple with memory cells of the second array in the corresponding rows.
11. The integrated chip according to claim 8 , wherein the first and second unipolar selectors have different dimensions.
12. The integrated chip according to claim 8 , wherein the first array comprises the memory cell, wherein the memory cell is electrically coupled to a conductive line of the plurality of first conductive lines, and wherein the bipolar selector is electrically separated from the conductive line by the data-storage element.
13. The integrated chip according to claim 12 , wherein the second array comprises an additional memory cell electrically coupled to the conductive line, wherein the additional memory cell comprises a second bipolar selector and a second data-storage element, and wherein the second data-storage element is electrically separated from the conductive line by the second bipolar selector.
14. The integrated chip according to claim 8 , wherein the plurality of first conductive lines comprises a conductive line in a column of the plurality of columns, and wherein the conductive line directly electrically couples to each memory cell of the first array in the column and further directly electrically couples to each memory cell of the second array in the column.
15. A method, comprising:
providing an array of memory cells having multiple rows and multiple columns, wherein the array comprises a memory cell in which a first unipolar selector and a second unipolar selector are electrically coupled in parallel with opposite orientations; and
reading the memory cell, wherein the first and second unipolar selectors are respectively ON and OFF while reading the memory cell, and wherein an ON resistance of the first unipolar selector is less than an ON resistance of the second unipolar selector.
16. The method according to claim 15 , wherein the memory cell comprises a data-storage element and further comprises a bipolar selector electrically coupled in series with the data-storage element, wherein the bipolar selector comprises the first unipolar selector and the second unipolar selector, and wherein the first unipolar selector has a different threshold voltage than a threshold voltage of the second unipolar selector.
17. The method according to claim 15 , wherein the reading comprises applying a read voltage more than a threshold voltage of the first unipolar selector across the memory cell at a first polarity, and wherein the first and second unipolar selectors are respectively ON and OFF while applying the read voltage across the memory cell.
18. The method according to claim 17 , further comprising:
applying a write voltage more than a threshold voltage of the second unipolar selector across the memory cell at a second polarity different than the first polarity, wherein the first and second unipolar selectors are respectively OFF and ON while applying the write voltage across the memory cell.
19. The method according to claim 15 , wherein the array comprises an additional memory cell in a same row as the memory cell and in a different column than the memory cell, and wherein a voltage across the additional memory cell is half a voltage across the memory cell during the reading.
20. The method according to claim 19 , wherein the additional memory cell comprises a third unipolar selector and a fourth unipolar selector electrically coupled in parallel with opposite orientations, and wherein the third and fourth unipolar selectors are OFF during the reading.