Semiconductor package and method of manufacturing semiconductor package
A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a first base with a first surface, in which a conductive pillar is arranged in the first base, the first surface includes a first groove, and the first groove exposes a top surface and a portion of a sidewall of the conductive pillar; a second base with a second surface, in which the first surface is bonded to the second surface, the second surface includes a second groove, an electrical connection pillar is arranged in the second base, the electrical connection pillar is located in the second groove, and the electrical connection pillar protrudes from the second surface; and an electrical connection structure, in which the electrical connection structure and a portion of the electrical connection pillar are embedded into the first groove.
1. A semiconductor structure, comprising:
a first base with a first surface, wherein a conductive pillar is arranged in the first base, the first surface comprises a first groove, and the first groove exposes a top surface and a portion of a sidewall of the conductive pillar;
a second base with a second surface, wherein the first surface is bonded to the second surface, the second surface comprises a second groove, an electrical connection pillar is arranged in the second base, the second groove is completely filled with the electrical connection pillar, and the electrical connection pillar protrudes from the second surface; and
an electrical connection structure, wherein the electrical connection structure and a portion of the electrical connection pillar are embedded into the first groove, and the electrical connection structure surrounds a portion of the conductive pillar exposed from the first groove and the portion of the electrical connection pillar embedded into the first groove.
2. The semiconductor structure according to claim 1 , wherein
in a plane perpendicular to a direction from the first surface to the second surface, a cross-sectional area of the electrical connection pillar is greater than a cross-sectional area of the conductive pillar.
3. The semiconductor structure according to claim 2 , wherein
a ratio of the cross-sectional area of the electrical connection pillar to the cross-sectional area of the conductive pillar ranges from 2 to 5.
4. The semiconductor structure according to claim 1 , wherein
in a direction perpendicular to a direction from the first surface to the second surface, a ratio of a width of the first groove to a width of the conductive pillar ranges from 2 to 3.
5. The semiconductor structure according to claim 1 , wherein
the electrical connection structure is located between the electrical connection pillar and the conductive pillar.
6. The semiconductor structure according to claim 1 , further comprising
a first protection layer located between the electrical connection structure and a surface collectively formed by the conductive pillar and the first groove.
7. The semiconductor structure according to claim 6 , further comprising
a first seed layer located between the first protection layer and the surface collectively formed by the conductive pillar and the first groove.
8. The semiconductor structure according to claim 1 , further comprising
a diffusion barrier layer located between an inner surface of the second groove and the electrical connection pillar, wherein a top surface of the diffusion barrier layer is higher than a top surface of the electrical connection pillar.
9. The semiconductor structure according to claim 8 , further comprising
a second seed layer located between the diffusion barrier layer and the electrical connection pillar, wherein a top surface of the second seed layer is flush with or lower than the top surface of the diffusion barrier layer.
10. The semiconductor structure according to claim 8 , wherein
the top surface of the electrical connection pillar and a portion of the diffusion barrier layer which is not in contact with the electrical connection pillar are configured to form a third groove.
11. The semiconductor structure according to claim 10 , further comprising
a second protection layer located at a bottom surface and a sidewall of the third groove, wherein a bottom surface and a sidewall of the second protection layer are configured to form a fourth groove, and a portion of the electrical connection structure is located in the fourth groove.
12. A method for manufacturing a semiconductor structure, comprising:
providing a first base with a first surface, wherein a conductive pillar is arranged in the first base, the first surface comprises a first groove, and the first groove exposes a top surface and a portion of a sidewall of the conductive pillar;
providing a second base with a second surface, wherein the second surface comprises a second groove;
forming an electrical connection pillar in the second groove;
forming an initial electrical connection structure on a side of the electrical connection pillar away from the second base; and
bonding the second surface comprising the electrical connection pillar and the initial electrical connection structure to the first surface, to embed the initial electrical connection structure and a portion of the electrical connection pillar into the first groove and to form an electrical connection structure;
wherein
providing the second base comprises:
providing an initial second base;
forming a mask layer with an opening on a surface of a side of the initial second base; and
etching the initial second base by using the mask layer as a mask to form the second base with the second groove;
wherein
forming the electrical connection pillar comprises forming the electrical connection pillar in the second groove and the opening, wherein the second groove is completely filled with the electrical connection pillar, and the electrical connection pillar is located in a portion of the opening.
13. The method for manufacturing the semiconductor structure according to claim 12 , wherein
before bonding the second surface to the first surface, the method further comprises forming a first protection layer on a surface collectively formed by the conductive pillar and the first groove.
14. The method for manufacturing the semiconductor structure according to claim 12 , wherein
before bonding the second surface to the first surface, the method further comprises: forming a first seed layer on a surface collectively formed by the conductive pillar and the first groove; and forming a first protection layer on a surface of the first seed layer.
15. The method for manufacturing the semiconductor structure according to claim 12 , wherein
in a direction from the first surface to the second surface, a ratio of a height of the electrical connection pillar located in the opening to a height of the mask layer ranges from 1/5 to 1/3.
16. The method for manufacturing the semiconductor structure according to claim 12 , wherein
before forming the electrical connection pillar, the method further comprises forming a diffusion barrier layer at a bottom portion and a sidewall of the second groove and a sidewall of the opening.
17. The method for manufacturing the semiconductor structure according to claim 16 , wherein
after forming the diffusion barrier layer, and before forming the electrical connection pillar, the method further comprises forming a second seed layer on a surface of the diffusion barrier layer.
18. The method for manufacturing the semiconductor structure according to claim 16 , wherein
a top surface of the electrical connection pillar and a portion of the diffusion barrier layer which is not in contact with the electrical connection pillar are configured to form a third groove, and wherein after forming the electrical connection pillar, and before forming the initial electrical connection structure, the method further comprises forming a second protection layer at a bottom surface and a sidewall of the third groove.