Protective structure with depletion-mode and enhancement-mode transistors
Disclosed are protective structures using depletion-mode and enhancement-mode transistors. A structure according to the disclosure may include a depletion-mode transistor having a gate coupled to ground and a first source/drain terminal. An enhancement-mode transistor includes a gate coupled to a second source/drain terminal of the depletion-mode transistor and a first source/drain terminal coupled to the gate of the depletion-mode transistor. The depletion-mode transistor limits a current flow from the first source/drain terminal to the gate of the enhancement-mode transistor.
1. A structure comprising:
a depletion-mode transistor having a gate coupled to ground and a first source/drain terminal; and
an enhancement-mode transistor having a gate coupled to a second source/drain terminal of the depletion-mode transistor and a first source/drain terminal coupled to the gate of the depletion-mode transistor.
2. The structure of claim 1 , wherein the first source/drain terminal of the depletion-mode transistor is coupled to an integrated circuit (IC) component.
3. The structure of claim 1 , wherein the depletion-mode transistor and the enhancement-mode transistor each include a high electron mobility transistor (HEMT) over a III-V semiconductor substrate.
4. The structure of claim 1 , wherein the depletion-mode transistor and the enhancement-mode transistor each include an aluminum gallium nitride (AlGaN) layer over a gallium nitride (GaN) layer such that an AlGaN/GaN interface is between the AlGaN layer and the GaN layer.
5. The structure of claim 1 , wherein the enhancement-mode transistor further includes a second source/drain terminal is decoupled from the first source/drain terminal of the depletion-mode transistor.
6. The structure of claim 1 , wherein the depletion-mode transistor comprises a portion of an electrostatic discharge (ESD) protective circuit.
7. The structure of claim 1 , wherein a pinch-off voltage of the depletion-mode transistor is at most approximately eight volts (V).
8. A structure comprising:
a depletion-mode transistor including a first gate coupled to an integrated circuit (IC) component, a first source, and a first drain; and
an enhancement-mode transistor including a second gate coupled to the first source, a second source coupled to the first gate through the IC component, and a second drain, wherein a composition of the first gate is different from a composition of the second gate.
9. The structure of claim 8 , wherein the depletion-mode transistor and the enhancement-mode transistor are each over a III-V semiconductor substrate.
10. The structure of claim 8 , wherein the depletion-mode transistor and the enhancement-mode HEMT each include an aluminum gallium nitride (AlGaN) layer over a gallium nitride (GaN) layer such that an AlGaN/GaN interface is between the AlGaN layer and the GaN layer.
11. The structure of claim 8 , wherein the second drain is decoupled from the IC component.
12. The structure of claim 8 , wherein the depletion-mode transistor comprises a portion of an electrostatic discharge (ESD) protective circuit.
13. The structure of claim 8 , wherein a pinch-off voltage of the depletion-mode transistor is at most approximately eight volts (V).
14. A structure comprising:
a first enhancement-mode transistor having a gate coupled to an integrated circuit (IC) component and a first source/drain terminal coupled to ground;
a second enhancement-mode transistor having a first source/drain terminal coupled to the IC component, a second source/drain terminal coupled to ground, and a gate terminal; and
a depletion-mode transistor having a first source/drain terminal coupled to a capacitor, a second source/drain terminal coupled to a resistor and the gate terminal of the second enhancement-mode transistor, and a gate terminal coupled to ground, wherein the resistor couples the gate terminal of the second enhancement-mode transistor and the second source/drain terminal of the depletion-mode transistor to gate of the depletion-mode transistor.
15. The structure of claim 14 , wherein the gate terminal of the depletion-mode transistor includes a different material composition from the gate terminal of the first enhancement-mode transistor and the second enhancement-mode transistor.
16. The structure of claim 14 , wherein the first enhancement-mode transistor, the second enhancement-mode transistor, and the depletion-mode transistor each include a high electron mobility transistor (HEMT) over a III-V semiconductor substrate.
17. The structure of claim 14 , wherein the first enhancement-mode transistor, the second enhancement-mode transistor, and the depletion-mode transistor each include an aluminum gallium nitride (AlGaN) layer over a gallium nitride (GaN) layer such that an AlGaN/GaN interface is between the AlGaN layer and the GaN layer.
18. The structure of claim 14 , wherein the first enhancement-mode transistor further includes a second source/drain terminal is decoupled from the IC component.
19. The structure of claim 14 , wherein the depletion-mode transistor comprises a portion of an electrostatic discharge (ESD) protective circuit.
20. The structure of claim 14 , wherein a pinch-off voltage of the depletion-mode transistor is at most approximately eight volts (V).