IP Library Granted Patent US 12,399,861
Granted Patent B1
US 12,399,861 · App. 18/533,951 · Granted Aug 26, 2025

Methods, systems, and computer readable media for applying digital signal processor (DSP) blocks in configurable sequences using sorting switch

Inventors: Allen Montijo (Colorado Springs, CO); Caleb Remington Begly (Colorado Springs, CO)
Assignee: KEYSIGHT TECHNOLOGIES, INC.
G06F15/82
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,399,861
App. No.
18/533,951
Granted
Aug 26, 2025
Kind
B1
Abstract

A method for applying digital signal processor (DSP) blocks in a configurable order includes providing a plurality of DSP blocks for performing a plurality of different signal processing operations on input data. The method further includes providing a sorting switch for connecting the DSP blocks together in a configurable order to implement a signal processing task. The method further includes configuring the sorting switch to apply the DSP blocks in a predetermined order to implement the signal processing task. The method further includes switching input data from the sorting switch to the DSP blocks in the predetermined order to implement the signal processing task.

Claims (24)

1. A method for applying digital signal processor (DSP) blocks in a configurable order, the method comprising:

providing a plurality of DSP blocks for performing a plurality of different signal processing operations on input data;

providing a sorting switch including a plurality of data input ports and a plurality of data output ports for connecting the DSP blocks together in a configurable order to implement a signal processing task, wherein each of the DSP blocks is connected to at least one of the data input ports of the sorting switch and at least one of the data output ports of the sorting switch and data flows from the data output ports of the sorting switch, through the DSP blocks, and back to the sorting switch via the data input ports;

configuring the sorting switch to apply the DSP blocks in a predetermined order to implement the signal processing task, wherein configuring the sorting switch to apply the DSP blocks includes writing values to control registers associated with the data input ports of the sorting switch that identify data output ports of the sorting switch to which data entering the sorting switch via the data input ports should be forwarded such that any of the DSP blocks is accessible via any of the data input ports; and

switching input data from the sorting switch to the DSP blocks in the predetermined order to implement the signal processing task.

2. The method of claim 1 wherein providing the DSP blocks includes providing DSP blocks for processing digitized data for an oscilloscope trace.

3. The method of claim 2 wherein providing the DSP blocks for processing the digitized data for the oscilloscope trace includes providing at least one arithmetic logic unit (ALU) block, at least one filter, at least one up converter, and at least one down converter.

4. The method of claim 1 wherein the sorting switch comprises a batcher switch.

5. The method of claim 4 wherein configuring the sorting switch includes configuring the batcher switch by writing the values to the control registers to control which ones of the DSP blocks are applied to the input data and the predetermined order in which the DSP blocks are applied to the input data.

6. The method of claim 4 wherein configuring the sorting switch includes configuring the batcher switch to apply different ones of the DSP blocks to different streams of input data.

7. The method of claim 4 wherein configuring the sorting switch includes configuring the sorting switch to split a stream of input data into two streams, process the streams using different ones of the DSP blocks, and combine the streams.

8. The method of claim 1 wherein switching the input data from the sorting switch to the DSP blocks includes forwarding the input data from the sorting switch to a first DSP block, from the first DSP block to the sorting switch, and from the sorting switch to a second DSP block.

9. The method of claim 1 comprising providing a plurality of the sorting switches and a plurality of the DSP blocks accessible via each of the sorting switches.

10. A system for applying digital signal processor (DSP) blocks in a configurable order, the system comprising:

a plurality of DSP blocks for performing a plurality of different signal processing operations on input data; and

a sorting switch including a plurality of data input ports and a plurality of data output ports for connecting the DSP blocks together, the sorting switch being configurable for applying the DSP blocks in a predetermined order to implement the signal processing task and for switching input data from the sorting switch to the DSP blocks in the predetermined order to implement the signal processing task, wherein each of the DSP blocks is connected to at least one of the data input ports of the sorting switch and at least one of the data output ports of the sorting switch and data flows from the data output ports of the sorting switch, through the DSP blocks, and back to the sorting switch via the data input ports and wherein the sorting switch is configurable to apply the DSP blocks by writing values to control registers associated with the data input ports of the sorting switch that identify data output ports of the sorting switch to which data entering the sorting switch via the data input ports should be forwarded such that any of the DSP blocks is accessible via any of the data input ports.

11. The system of claim 10 wherein the DSP blocks are configured to process digitized data for an oscilloscope trace.

12. The system of claim 11 wherein the DSP blocks include at least one arithmetic logic unit (ALU) block, at least one filter, at least one up converter, and at least one down converter.

13. The system of claim 10 wherein the sorting switch comprises a batcher switch.

14. The system of claim 13 wherein the batcher switch is configurable by writing the values to the control registers to control which ones of the DSP blocks are applied to the input data and the predetermined order in which the DSP blocks are applied to the rut data.

15. The system of claim 13 wherein the batcher switch is configurable to apply different ones of the DSP blocks to different streams of input data.

16. The system of claim 13 wherein the batcher switch is configurable to split a stream of input data into two streams, process the streams using different ones of the DSP blocks, and combine the streams.

17. The system of claim 10 wherein the sorting switch is configurable to switch the input data from the sorting switch to a first DSP block, from the first DSP block to the sorting switch, and from the sorting switch to a second DSP block.

18. The system of claim 10 comprising a plurality of the sorting switches and a plurality of the DSP blocks accessible via each of the sorting switches.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2023
From: MONTIJO, ALLEN; BEGLY, CALEB REMINGTON
To: KEYSIGHT TECHNOLOGIES, INC.
Reel/Frame 065829/0359 →
References Cited (32)
US 4516238A · Huang · 1985 [cited by examiner]
US 5630153A · Intrater et al. · 1997 [cited by applicant]
US 7193435B2 · Grabill et al. · 2007 [cited by applicant]
US 7729459B1 · Kang et al. · 2010 [cited by applicant]
US 8290758B2 · Aarts et al. · 2012 [cited by applicant]
US 8355507B1 · Beffa · 2013 [cited by examiner]
US 8989329B2 · Hammad et al. · 2015 [cited by applicant]
US 10673440B1 · Camarota · 2020 [cited by examiner]
US 11119929B2 · Barner · 2021 [cited by examiner]
US 11169822B2 · Camarota · 2021 [cited by examiner]
US 11323354B1 · Sommers · 2022 [cited by applicant]
US 11336287B1 · Rodriguez · 2022 [cited by examiner]
US 11507531B2 · Luo · 2022 [cited by examiner]
US 11520717B1 · Clarke · 2022 [cited by examiner]
US 20100097979A1 · Shinozaki · 2010 [cited by applicant]
US 20140133614A1 · Huntley et al. · 2014 [cited by applicant]
US 20150100622A1 · Urban et al. · 2015 [cited by applicant]
US 20160196940A1 · Becker · 2016 [cited by examiner]
US 20170135676A1 · Rothberg · 2017 [cited by examiner]
US 20210013885A1 · Atsatt · 2021 [cited by examiner]
US 20220196735A1 · Atsatt · 2022 [cited by examiner]
US 20220397589A1 · Stein · 2022 [cited by applicant]
Commonly-assigned, co-pending U.S. Appl. No. 18/395,193 “Applying Digital Signal Processor (DSP) Blocks for Error Detection and Eye Diagram Generation” (Unpublished, Dec. 22, 2023). [cited by applicant]
Commonly-assigned, co-pending U.S. Appl. No. 18/392,598 for “Methods, Systems, and Computer Readable Media for Providing a Network Test Environment With Mismatch Mediation Functionality” (Unpublished, filed Dec. 28, 202… [cited by applicant]
How Do Measure the Bit Error Rate (BER) to a Given Confidence Level on the JBERTM8020A and the M8040A High-Performance BERT? Keysight Technologies, Inc. (Oct. 10, 2023). [cited by applicant]
Infiniium MXR-Series Data Sheet—pp. 1-45 Keysight Technologies, Inc. (Jun. 20, 2023). [cited by applicant]
Gao, Susan et al., “A novel architecture of recovered data comparison for high speed clock and data recovery,” Stevens Institute of Technology, Proc. SPIE 5847, Noise in Communication Systems, pp. 179-187 (May 23, 2005). [cited by applicant]
Musa, Faisal A., “High-Speed Baud-Rate Clock Recovery,” University of Toronto, pp. 1-141 (2008). [cited by applicant]
Moon, Un-Ku, et al, “Timing Recovery in CMOS using Nonlinear Spectral-line Method,” AT&T Bell Laboratories, IEEE 1996 Custom Integrated C1 Rcuits Conference, pp. 13-16 (1996). [cited by applicant]
Bailey et al., “A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance”, IEEE Journal of Solid-State Circuits, vol. 54 No. 10, pp. 1-16 (Oct. 2019). [cited by applicant]
Matthew Caesar, “Lecture 7: Switches”, CS/ECE 438: Communication Networks, pp. 1-43 (Feb. 26, 2010). [cited by applicant]
“Example of Batcher Network for High Speed ATM Switch”, http://doctord.webhop.net/courses/topics/networks/Topology/batcher.html, (Aug. 28, 2000). [cited by applicant]