Error correction based on asymmetric ratio
Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.
1. A method for decoding a low-density parity check (LDPC) codeword by a bit flipping (BF) decoder, the method comprising:
receiving a signal comprising bit data representing the LDPC codeword from a memory channel; and
during an iteration of decoding in a decoding attempt:
determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one;
computing an energy of each variable node of the LDPC codeword;
for each variable node having an energy greater than a threshold energy, adding the variable node to a collection of candidate bits for bit flipping; and
applying the asymmetric ratio to flip bits in the collection of candidate bits to decode the LDPC codeword.
2. The method of claim 1 , wherein the collection of candidate bits includes a set of candidate bits read as logic zero, and a set of candidate bits read as logic one.
3. The method of claim 2 , wherein when the set of candidate bits read as logic zero has fewer number of candidate bits than multiplying the asymmetric ratio to a number of candidate bits in the set of candidate bits read as logic one, the asymmetric ratio is applied by:
flipping all bits in the set of candidate bits read as logic zero; and
randomly flipping the asymmetric ratio number of bits in the set of candidate bits read as logic one.
4. The method of claim 2 , wherein when the set of candidate bits read as logic zero has equal or greater number of candidate bits than multiplying the asymmetric ratio to a number of candidate bits in the set of candidate bits read as logic one, the asymmetric ratio is applied by:
flipping all bits in the set of candidate bits read as logic one; and
randomly flipping the asymmetric ratio number of bits in the set of candidate bits read as logic zero.
5. The method of claim 1 , wherein the iteration of decoding is performed after a threshold number of previous decoding iterations have been performed without applying the asymmetric ratio.
6. The method of claim 5 , further comprising:
for each of the previous decoding iterations:
storing a checksum of the previous decoding iteration;
storing a number of variable nodes read as logic zero and having a hard decision of being logic one; and
storing a number of variable nodes read as logic one and having a hard decision of being logic zero.
7. The method of claim 6 , wherein the asymmetric ratio is determined based on the checksum, the number of variable nodes read as logic zero and having a hard decision of being logic one, and the number of variable nodes read as logic one and having a hard decision of being logic zero.
8. The method of claim 7 , wherein the asymmetric ratio is determined when the number of 1's in the checksum of an iteration is less than half the number of 1's in an initial checksum.
9. The method of claim 8 , wherein the asymmetric ratio is determined as:
α
ˆ
r
=
C
i
1
→
0
*
(
n
-
n
1
)
C
i
0
→
1
*
n
1
in which {circumflex over (α)} r is the asymmetric ratio, C i 1→0 is the number of variable nodes read as logic one and having a hard decision of being logic zero, C i 0→1 is the number of variable nodes read as logic zero and having a hard decision of being logic one, n is the total number of bits read, n 1 is the total number of bits read as logic one.
10. The method of claim 7 , wherein the asymmetric ratio is determined by a neural network model trained on the checksum, the number of variable nodes read as logic zero and having a hard decision of being logic one, and the number of variable nodes read as logic one and having a hard decision of being logic zero.
11. The method of claim 1 , further comprising performing another decoding attempt when the asymmetric ratio is greater than a threshold value or less than a reciprocal of the threshold value.
12. A device comprising:
a memory storing a low-density parity-check (LDPC) codeword; and
one or more processing units configured to:
receive a signal comprising bit data representing the LDPC codeword from a memory channel; and
perform operations during an iteration of decoding in a decoding attempt, the operations including:
determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one;
computing an energy of each variable node of the LDPC codeword;
for each variable node having an energy greater than a threshold energy, adding the variable node to a collection of candidate bits for bit flipping; and
applying the asymmetric ratio to flip bits in the collection of candidate bits to decode the LDPC codeword.
13. The device of claim 12 , wherein the collection of candidate bits includes a set of candidate bits read as logic zero, and a set of candidate bits read as logic one.
14. The device of claim 13 , wherein when the set of candidate bits read as logic zero has fewer number of candidate bits than multiplying the asymmetric ratio to a number of candidate bits in the set of candidate bits read as logic one, the asymmetric ratio is applied by:
flipping all bits in the set of candidate bits read as logic zero; and
randomly flipping the asymmetric ratio number of bits in the set of candidate bits read as logic one.
15. The device of claim 13 , wherein when the set of candidate bits read as logic zero has equal or greater number of candidate bits than multiplying the asymmetric ratio to a number of candidate bits in the set of candidate bits read as logic one, the asymmetric ratio is applied by:
flipping all bits in the set of candidate bits read as logic one; and
randomly flipping the asymmetric ratio number of bits in the set of candidate bits read as logic zero.
16. The device of claim 12 , wherein the iteration of decoding is performed after a threshold number of previous decoding iterations have been performed without applying the asymmetric ratio.
17. The device of claim 12 , wherein the asymmetric ratio is determined when the number of 1's in a checksum of the iteration is less than half the number of 1's in an initial checksum, and wherein the asymmetric ratio is determined based on the checksum of the iteration, a number of variable nodes read as logic zero and having a hard decision of being logic one, and a number of variable nodes read as logic one and having a hard decision of being logic zero.
18. The device of claim 17 wherein the asymmetric ratio is determined as:
α
ˆ
r
=
C
i
1
→
0
*
(
n
-
n
1
)
C
i
0
→
1
*
n
1
in which {circumflex over (α)} r is the asymmetric ratio, C i 1→0 is the number of variable nodes read as logic one and having a hard decision of being logic zero, C i 0→1 is the number of variable nodes read as logic zero and having a hard decision of being logic one, n is the total number of bits read, n 1 is the total number of bits read as logic one.
19. The device of claim 17 , wherein the asymmetric ratio is determined by a neural network model trained on the checksum, the number of variable nodes read as logic zero and having a hard decision of being logic one, and the number of variable nodes read as logic one and having a hard decision of being logic zero.
20. The device of claim 12 , wherein the operations include performing another decoding attempt when the asymmetric ratio is greater than a than a threshold value or less than a reciprocal of the threshold value.