Superscalar execution using pipelines that support different precisions
View Patent ↗Techniques are disclosed relating to scheduling instructions for floating-point execution units with different capabilities. In some embodiments, a first pipeline is configured to execute a first type of floating-point operation on operands having up to a first precision and a second pipeline is configured to execute the first type of floating-point operation on operands having up to a second, greater precision. In some embodiments, round circuitry is configured to round results from an output precision of the second pipeline to an output precision of the first pipeline. Scheduling circuitry may select operations for issuance for a given cycle from multiple ready threads. This may include to prioritize a determined highest-precision operation of the first type from ready operations and assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.
1. An apparatus, comprising:
pipeline circuitry that includes multiple pipelines, including:
a first pipeline configured to execute a first type of operation on operands having up to a first precision; and
a second pipeline configured to execute the first type of operation on operands having up to a second precision that is greater than the first precision;
scheduling circuitry configured to select operations for issuance to the multiple pipelines, for a given cycle from multiple ready threads, including to:
prioritize a determined highest-precision operation of the first type from ready operations; and
assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.
2. The apparatus of claim 1 , wherein the first type of operation is a floating-point operation, the apparatus further comprising:
round circuitry configured to round results from an output precision of the second pipeline to an output precision of the first pipeline.
3. The apparatus of claim 2 , wherein the round circuitry is configured to:
round to generate a rounded result that matches numerically with a result that would have been generated for the operation by the first pipeline, including to:
round an output of the second pipeline to odd to generate an initial rounding result in the second precision; and
round the initial rounding result to generate a result for the first type of floating-point operation in the first precision.
4. The apparatus of claim 2 , wherein the floating-point operation is a fused multiply-add.
5. The apparatus of claim 1 , wherein:
the second pipeline is configured to execute the first type of operation with all input operands having the second precision; and
the multiple pipelines further include a third pipeline that is configured to execute the first type of operation of which a subset of input operands have the second precision and a subset of input operands have the first precision.
6. The apparatus of claim 5 , wherein:
the first pipeline is configured to provide a 16-bit fused multiply-add result based on three 16-bit input operands;
the third pipeline is configured to provide a 32-bit fused multiply-add result based on 16-bit multiplicands and a 32-bit addend; and
the second pipeline is configured to provide a 32-bit fused multiply-add result based on at least one 32-bit multiplicand.
7. The apparatus of claim 1 , wherein the multiple pipelines include multiple pipelines having the same precision.
8. The apparatus of claim 1 , wherein the scheduling circuitry is configured to select from instructions for issuance from an instruction window that includes a set of multiple oldest available instructions.
9. The apparatus of claim 1 , wherein the apparatus is a computing device that further includes:
a display; and
network interface circuitry.
10. The apparatus of claim 1 , wherein the apparatus includes:
a plurality of single-instruction multiple-data pipelines configured to execute instructions; and
fixed-function circuitry configured to control the single-instruction multiple-data pipelines to perform operations for at least one of the following types of programs:
graphics shader programs; and
machine learning programs.
11. A method, comprising:
selecting operations from multiple ready threads for issuance to multiple pipelines, for a given cycle, wherein:
a first pipeline of the multiple pipelines is configured to execute a first type of operation on operands having up to a first precision;
a second pipeline of the multiple pipelines is configured to execute the first type of operation on operands having up to a second precision that is greater than the first precision; and
the selecting includes:
prioritizing a determined highest-precision operation of the first type from ready operations; and
assigning the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.
12. The method of claim 11 , further comprising:
rounding a result from an output precision of the second pipeline to an output precision of the first pipeline, including:
rounding an output of the second pipeline to odd to generate an initial rounding result in the second precision; and
rounding the initial rounding result to generate a result for the first type of floating-point operation in the first precision.
13. The method of claim 11 , wherein:
the second pipeline is configured to execute the first type of operation with all input operands having the second precision; and
the multiple pipelines further include a third pipeline that is configured to execute the first type of operation of which a subset of input operands have the second precision and a subset of input operands have the first precision.
14. The method of claim 13 , wherein:
the first pipeline is configured to provide a 16-bit fused multiply-add result based on three 16-bit input operands;
the third pipeline is configured to provide a 32-bit fused multiply-add result based on 16-bit multiplicands and a 32-bit addend; and
the second pipeline is configured to provide a 32-bit fused multiply-add result based on at least one 32-bit multiplicand.
15. The method of claim 11 , wherein the multiple pipelines include multiple pipelines having the same floating-point precision.
16. The method of claim 11 , wherein the selecting selects from instructions for issuance from an instruction window that includes a set of multiple oldest available instructions.
17. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
pipeline circuitry that includes multiple pipelines, including:
a first pipeline configured to execute a first type of operation on operands having up to a first precision; and
a second pipeline configured to execute the first type of operation on operands having up to a second precision that is greater than the first precision;
scheduling circuitry configured to select operations for issuance to the multiple pipelines, for a given cycle from multiple ready threads, including to:
prioritize a determined highest-precision operation of the first type from ready operations; and
assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.
18. The non-transitory computer readable storage medium of claim 17 , wherein the first type of operation is a floating-point operation, the circuit further comprising:
round circuitry configured to round results from an output precision of the second pipeline to an output precision of the first pipeline such that a rounded result matches numerically with a result that would have been generated for the operation by the first pipeline.
19. The non-transitory computer readable storage medium of claim 17 , wherein:
the second pipeline is configured to execute the first type of operation with all input operands having the second precision; and
the multiple pipelines further include a third pipeline that is configured to execute the first type of floating-point operation of which a subset of input operands have the second precision and a subset of input operands have the first precision;
the first pipeline is configured to provide a 16-bit fused multiply-add result based on three 16-bit input operands;
the third pipeline is configured to provide a 32-bit fused multiply-add result based on 16-bit multiplicands and a 32-bit addend; and
the second pipeline is configured to provide a 32-bit fused multiply-add result based on at least one 32-bit multiplicand.
20. The non-transitory computer readable storage medium of claim 19 , wherein the scheduling circuitry is configured to select from instructions for issuance from an instruction window that includes a set of multiple oldest available instructions.