Systems and methods for mapping matrix calculations to a matrix multiply accelerator
Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
1. A method of configuring an integrated circuit with coefficient values, the method comprising:
identifying a coefficient mapping technique based on attributes of two or more computational algorithms;
configuring a plurality of processing circuits of the integrated circuit with coefficient values of the two or more computational algorithms based on the identified coefficient mapping technique,
wherein the identified coefficient mapping technique includes mapping a set of coefficients of a first algorithm of the two or more computational algorithms to a first set of processing circuits of the plurality of processing circuits and mapping a second set of coefficients of a second algorithm of the two or more computational algorithms to a second set of processing circuits of the plurality of processing circuits, and
wherein identifying the coefficient mapping technique is based on identifying that a computation of at least one of the sets of coefficients of the first algorithm and the second algorithm requires fewer outputs than an output capacity of the plurality of processing circuits.
2. The method according to claim 1 , further comprising:
if the first set of processing circuits and the second set of processing circuits have (a) nonoverlapping input ports and (b) overlapping output ports:
configuring the integrated circuit to execute, at runtime, one of the first set of processing circuits and the second set of processing circuits while deactivating one of the first set of processing circuits and the second set of processing circuits that is not executed.
3. The method according to claim 1 , further comprising:
at runtime, executing one of the first set of processing circuits and the second set of processing circuits while deactivating one of the first set of processing circuits and the second set of processing circuits that is not executed.
4. The method according to claim 1 , wherein
identifying the coefficient mapping technique is based on identifying that a computation of the sets of coefficients of the first algorithm and the second algorithm in combination require fewer inputs and fewer outputs than an input capacity and a plurality output capacity of the plurality of processing circuits.
5. The method according to claim 1 , wherein:
regions of the sets of coefficients of the first algorithm and the second algorithm of the plurality of processing circuits are non-overlapping regions and each have nonoverlapping input ports and nonoverlapping output ports;
the method further comprises:
configuring the integrated circuit to execute, at runtime, the regions of the sets of coefficients of the first algorithm and the second algorithm in parallel.
6. The method according to claim 1 , wherein
regions of the sets of coefficients of the first algorithm and the second algorithm of the plurality of processing circuits have partially overlapping input regions are and have nonoverlapping output ports.
7. The method according to claim 1 , wherein:
the set of coefficients of each of the first algorithm and the second algorithm are arranged in parallel and are arranged along nonoverlapping output ports; and
configuring the integrated circuit to implement, at runtime, an input/output handling technique that includes:
setting a multiplexor to serially output computation results of each of the first algorithm and the second algorithm via an overlapping output circuit.
8. The method according to claim 1 , further comprising:
configuring the plurality of processing circuits to produce positive outputs and produce negative logical outputs based on input signals into the plurality of processing circuits includes:
configuring one or more plurality coefficient input locations within the plurality of processing circuits with a positive line that passes an input signal with a positive sign and a negative line that passes an input signal with a negative sign; and
setting a coefficient along each of the positive line and the negative line of the one or more plurality coefficient input locations.
9. The method according to claim 1 , wherein:
if an input vector into the plurality of processing circuits includes a greater bit-size than a bit-size of a plurality coefficient input location within the plurality of processing circuits, the coefficient mapping technique includes:
prior to receiving bits of an input vector having oversized input bits, shifting coefficients of an undersized plurality coefficient input location to multiple rows of the plurality of processing circuits,
the method further comprising:
configuring the integrated circuit to:
spread, at runtime, bits of the input vector over the multiple rows of the plurality of processing circuits; and
sum, at runtime, outputs of the multiple rows of the plurality of processing circuits that share a coefficient value that is overlapping.
10. The method according to claim 1 , wherein:
if an input vector into the plurality of processing circuits includes a greater bit-size than a bit-size of a coefficient input location within the plurality of processing circuits, configuring the integrated circuit to implement, at runtime, an input/output handling technique that includes:
partitioning bits of the input vector having oversized input bits over multiple calculations of the plurality of processing circuits in a serial manner or stepped fashion; and
the method further comprising:
configuring the integrated circuit to shift, at runtime, outputs of the multiple calculations of the plurality of processing circuits into an alignment prior to summing output values of the multiple calculations.
11. A method of configuring an integrated circuit with coefficient values, the method comprising:
identifying a coefficient mapping technique based on attributes of a plurality of distinct algorithms;
configuring the plurality of processing circuits of the integrated circuit with coefficient values of the plurality of distinct algorithms based on the identified coefficient mapping technique, wherein the identified coefficient mapping techniques include:
mapping coefficients of each of the plurality of distinct algorithms to a plurality of distinct regions of the plurality of processing circuits; and
configuring the integrated circuit to serially execute, at runtime, each of the plurality of distinct regions of the plurality of processing circuits.
12. The method according to claim 11 , further comprising:
configuring the integrated circuit to select, at runtime, one or more of the plurality of distinct regions having nonoverlapping output ports for active execution and disabling an execution of remaining distinct regions of the plurality of distinct regions.
13. The method according to claim 11 , wherein
identifying the coefficient mapping technique is based on identifying that a combination of the plurality of distinct algorithms require fewer inputs and fewer outputs than an input capacity and an output capacity of the plurality of processing circuits.
14. A method of configuring an integrated circuit with coefficient values, the method comprising:
identifying a coefficient mapping technique based on attributes of two or more computational algorithms;
configuring the plurality of processing circuits of the integrated circuit with coefficient values of the two or more computational algorithms based on the identified coefficient mapping technique, wherein the identified coefficient mapping techniques includes:
partitioning coefficient values of the two or more computational algorithms to multiple distinct pluralities of processing circuits;
applying an input vector to each of the multiple distinct pluralities of processing circuits; and
combining outputs of the multiple distinct pluralities of processing circuits.
15. The method according to claim 14 , wherein
identifying the coefficient mapping technique is based on identifying that a computation of at least one of the two or more computational algorithms require greater inputs than an input capacity and/or greater outputs than an output capacity of the plurality of processing circuits.
16. The method according to claim 14 , further comprising:
configuring the plurality of processing circuits to produce positive outputs and produce negative logical outputs based on input signals into the plurality of processing circuits includes:
configuring one or more plurality coefficient input locations within the plurality of processing circuits with a positive line that passes an input signal with a positive sign and a negative line that passes an input signal with a negative sign; and
setting a coefficient along each of the positive line and the negative line of the one or more plurality coefficient input locations.
17. The method according to claim 14 , wherein:
if an input vector into the plurality of processing circuits includes a greater bit-size than a bit-size of a coefficient input location within the plurality of processing circuits, the coefficient mapping technique includes:
prior to receiving bits of an input vector having oversized input bits, shifting coefficients of an undersized plurality coefficient input location to multiple rows of the plurality of processing circuits,
the method further comprising:
configuring the integrated circuit to:
spread, at runtime, bits of the input vector over the multiple rows of the plurality of processing circuits; and
sum, at runtime, outputs of the multiple rows of the plurality of processing circuits that share a coefficient value that is overlapping.
18. The method according to claim 14 , wherein:
if an input vector into the plurality of processing circuits includes a greater bit-size than a bit-size of a coefficient input location within the plurality of processing circuits, configuring the integrated circuit to implement, at runtime, an input/output handling technique that includes:
partitioning bits of the input vector having oversized input bits over multiple calculations of the plurality of processing circuits in a serial manner or stepped fashion; and
the method further comprising:
configuring the integrated circuit to shift, at runtime, outputs of the multiple calculations of the plurality of processing circuits into an alignment prior to summing output values of the multiple calculations.