Memory device with unipolar selector
View Patent ↗Various embodiments of the present application are directed towards a method of forming a memory device. The method includes forming a lower part of an interconnect structure over a substrate and forming a unipolar selector over the lower part of the interconnect structure. The method further comprises forming a data-storage element over the unipolar selector and electrically coupled in series with the unipolar selector, the data-storage element having a variable resistance. The method further comprises generating an external magnetic field by a magnetic field generator to pre-set the data-storage element to a first data state.
1. A method of forming an integrated chip, comprising:
forming a first memory array over a substrate and comprising a first plurality of memory cells arranged in rows and columns, wherein the first plurality of memory cells respectively comprises a unipolar selector and a data-storage element electrically coupled in series with a current path across the data-storage element in one way, wherein the data-storage element is configured to be set from a first data state to a second data state by applying a writing voltage across the data-storage element;
forming a first plurality of bit lines extending along corresponding rows of first the memory array and respectively connected to first terminals of the first plurality of memory cells in the corresponding rows;
forming a first plurality of source lines extending along corresponding columns of the first memory array and respectively connected to second terminals of the first plurality of memory cells in the corresponding columns; and
forming a magnetic field generator coupled to the first memory array and configured to generate an external magnetic field to set the data-storage element to the first data state.
2. The method according to claim 1 , wherein forming the magnetic field generator comprises forming a current carrying wire coupled to a controller and configured to generate a magnetic field that simultaneously resets the data-storage element of each of the first plurality of memory cells.
3. The method according to claim 1 ,
wherein the data-storage element is a magnetic tunnel junction (MTJ) comprising a reference ferromagnetic element and a free ferromagnetic element separated by a tunneling barrier layer.
4. The method according to claim 1 , further comprising:
forming a second memory array stacked over the first memory array and comprising a second plurality of memory cells arranged in rows and columns, wherein the second plurality of memory cells respectively comprises a unipolar selector and a data-storage element electrically coupled in series;
forming a second plurality of bit lines extending along corresponding rows of the second memory array and electrically coupled with first terminals of the second plurality of memory cells in the corresponding rows; and
forming a second plurality of source lines extending along corresponding columns of the second memory array and respectively connected with second terminals of the second plurality of memory cells in the corresponding columns.
5. The method according to claim 4 , wherein the first memory array and the second memory array are embedded in a logic circuit disposed on the substrate.
6. The method according to claim 1 , further comprising:
forming a second memory array comprising a second plurality of memory cells arranged in rows and columns, wherein the second plurality of memory cells respectively comprises a unipolar selector and a data-storage element electrically coupled in series; and
forming a second plurality of bit lines extending along corresponding rows of the second memory array and electrically coupled with first terminals of the second plurality of memory cells in the corresponding rows; and
wherein the first plurality of source lines also extends along corresponding columns of the second memory array and electrically coupled with second terminals of the memory cells of the second memory array in the corresponding columns.
7. The method according to claim 6 ,
wherein anodes of unipolar selectors of the first memory array are connected to the first plurality of bit lines, and wherein cathodes of the unipolar selectors of the first memory array are connected to first terminals of the data-storage element of the first memory array;
wherein the anodes of the unipolar selectors of the second memory array are connected to the second plurality of bit lines, and wherein the cathodes of the unipolar selectors of the second memory array are connected to first terminals of the data-storage elements of the second memory array; and
wherein second terminals of the data-storage elements of the first memory array and the second memory array are respectively connected to the first plurality of source lines.
8. A method of forming an integrated chip, comprising:
forming a memory array over a substrate and comprising a plurality of memory cells arranged in rows and columns, wherein the plurality of memory cells respectively comprises:
a lower part of an interconnect structure over the substrate;
a unipolar selector over the lower part of the interconnect structure; and
a data-storage element over the unipolar selector and electrically coupled in series with the unipolar selector, the data-storage element having a variable resistance; and
generating an external magnetic field by a magnetic field generator to set the data-storage element to a first data state,
wherein the plurality of memory cells is configured to be written from the first data state to a second data state by a single polarity writing voltage applied across the data-storage element and the unipolar selector.
9. The method according to claim 8 , further comprising:
forming a bit line wire in the lower part of the interconnect structure; and
forming a via on the bit line wire,
wherein the unipolar selector is formed with an anode connected to the bit line wire through the via and a cathode connected to one end of the data-storage element.
10. The method according to claim 9 , further comprising forming a source line wire overlying the data-storage element and connected to the other end of the data-storage element.
11. The method according to claim 8 , wherein the unipolar selector and the data-storage element are electrically coupled with a current path across the data-storage element in one way, wherein the plurality of memory cells is absent of any selector coupled to the data-storage element with an opposite current path across the data-storage element in the other way.
12. The method according to claim 11 , wherein the data-storage element is configured to be read by applying a reading voltage across the data-storage element and the unipolar selector.
13. The method according to claim 8 , wherein the data-storage element is a magnetic tunnel junction (MTJ) formed with a reference ferromagnetic element and a free ferromagnetic element separated by a tunneling barrier layer.
14. The method according to claim 13 ,
wherein a cathode of the unipolar selector is directly connected to the reference ferromagnetic element of the MTJ;
wherein an anode of the unipolar selector is directly connected to a source line; and
wherein the free ferromagnetic element of the MTJ is directly connected to a bit line.
15. The method according to claim 8 , wherein the unipolar selector is a PIN diode.
16. A method of forming an integrated chip, comprising:
forming a memory array comprising a plurality of memory cells arranged in rows and columns, wherein the plurality of memory cells respectively comprises a unipolar selector and a data-storage element electrically coupled in series; and
generating an external magnetic field by a magnetic field generator to set the data-storage element to a first data state,
wherein the unipolar selector and the data-storage element are electrically coupled with a current path across the data-storage element in one way, wherein the plurality of memory cells is absent of any selector coupled to the data-storage element with a opposite current path across the data-storage element in the other way, and
wherein the plurality of memory cells is configured to be written from the first data state to a second data state by applying a writing voltage of a first polarity across the data-storage element and the unipolar selector of a selected memory cell.
17. The method according to claim 16 ,
wherein unselected memory cells are biased at a second polarity opposite to the first polarity when applying the writing voltage across the selected memory cell.
18. The method according to claim 17 , wherein the unselected memory cells are reversely biased by an inhibiting voltage having an absolute value that is equal to that of the writing voltage.
19. The method according to claim 16 , wherein the magnetic field generator is off-board of the integrated chip.
20. The method according to claim 16 , wherein the magnetic field generator is a current carrying wire that is magnetically coupled to the data-storage elements of the plurality of memory cells.