IP Library Granted Patent US 12,406,921
Granted Patent B2
US 12,406,921 · App. 17/870,676 · Granted Sep 2, 2025

Electronic device

Inventors: Jung Jui Kang (Kaohsiung, TW); Chang Chi Lee (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/5226H01L23/3128H01L23/49816H01L23/50H01L23/5286H01L24/13H01L24/19H01L2224/12105H01L2224/18
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Quick Facts
Patent No.
US 12,406,921
App. No.
17/870,676
Granted
Sep 2, 2025
Kind
B2
Abstract

An electronic device is disclosed. The electronic device includes a first circuit structure, a first die, a second die, and a third die. The first die is disposed below the first circuit structure. The second die is disposed below the first circuit structure. The third die is disposed above the first circuit structure and electrically connects the first die to the second die. The first die communicates with the second die through the third die.

Claims (39)

1. An electronic device, comprising:

a first circuit structure;

a first die disposed below the first circuit structure;

a second die disposed below the first circuit structure; and

a third die disposed above the first circuit structure and electrically connecting the first die to the second die,

wherein the first die communicates with the second die through the third die,

wherein the first die includes an active surface facing the first circuit structure and a backside surface opposite to the active surface of the first die, wherein the first die is configured to receive a power through the backside surface thereof.

2. The electronic device of claim 1 , wherein the third die is a data storage unit, wherein the first die is configured to access data in the third die.

3. The electronic device of claim 2 , wherein the second die is a Serializer/Deserializer (SerDes).

4. The electronic device of claim 1 , wherein a non-power signal transmission path is provided along a lateral surface of the first die and in the first circuit structure, and wherein a non-power signal is transmitted to an active circuit adjacent to the active surface of the first die through the non-power signal transmission path.

5. The electronic device of claim 1 , further comprising:

a second circuit structure having a first region and a second region distinct from the first region,

wherein the first region of the second circuit structure is configured to transmit a non-power signal to the first die through the first circuit structure, and

wherein the second region of the second circuit structure is configured to transmit the power to the first die through the backside surface of the first die.

6. The electronic device of claim 5 , wherein the first region is uncovered by the first die, and wherein the second region is disposed under the first die.

7. The electronic device of claim 6 , wherein the first die includes a first conductive via extending through the first die, and wherein the second region comprises a second conductive via electrically connected to the first conductive via.

8. The electronic device of claim 7 , wherein a width of the first conductive via is less than that of the second conductive via.

9. The electronic device of claim 5 , wherein the second circuit structure further has a third region configured to dissipate heat from the second die.

10. The electronic device of claim 1 , wherein a data transmission path consists of a first signal path from the first die to the third die, a second signal path from the third die to the second die, and a third signal path in the third die, wherein the third signal path connects the first signal path with the second signal path.

11. The electronic device of claim 1 , wherein the second die is disposed adjacent to the first die,

wherein the third die is configured to transmit a non-power signal from the first die to the second die, wherein data stored in the third die is configured to be accessed by the first die.

12. The electronic device of claim 11 , wherein the first circuit structure is configured to provide a first data transmission path for transmitting a first non-power signal to the first die;

wherein the first circuit structure is configured to provide a second data transmission path for transmitting a second non-power signal between the first die and the third die; and

wherein the first circuit structure is configured to provide a third data transmission path for transmitting a third non-power signal between the third die and the second die.

13. The electronic device of claim 11 , further comprising:

a second circuit structure comprising a power via and a non-power via,

wherein the power via is disposed under the first die, and the non-power via is uncovered by the first die.

14. The electronic device of claim 13 , wherein a width of the power via is greater than that of the non-power via.

15. The electronic device of claim 13 , wherein a pitch of the power via is greater than that of the non-power via.

16. The electronic device of claim 13 , wherein the second circuit structure further comprises a thermal via disposed under the second die, wherein a width of the thermal via is greater than that of the power via.

17. The electronic device of claim 1 ,

wherein the second die has an active surface facing the third die and communicates with the first die through the third die; and

wherein the electronic device comprises a carrier configured to provide the power to the first die and dissipate heat from the second die.

18. The electronic device of claim 17 , further comprising:

a passive component disposed under the first die and configured to stabilize the power and filter noise from the power.

19. The electronic device of claim 17 , further comprising:

an encapsulating layer encapsulating the first die and the second die,

wherein the first die comprises a circuit disposed under the backside surface of the first die, and the circuit is configured to stabilize the power and filter noise from the power, and

wherein the circuit is encapsulated by the encapsulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2022
From: KANG, JUNG JUI; LEE, CHANG CHI
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 060776/0343 →
Continuity (1)
Related Publication 20240030125A1 · Jan 25, 2024
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