IP Library Granted Patent US 12,407,621
Granted Patent B2
US 12,407,621 · App. 17/550,938 · Granted Sep 2, 2025

Path selection for packet transmission

Inventors: Anurag Agrawal (Santa Clara, CA); John Andrew Fingerhut (Cary, NC); Xiaoyan Ding (Lantau Island, HK); Song Zhang (Beijing, CN)
Assignee: Intel Corporation
H04L47/628H04L45/24H04L49/3063
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Quick Facts
Patent No.
US 12,407,621
App. No.
17/550,938
Granted
Sep 2, 2025
Kind
B2
Abstract

Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

Claims (49)

1. At least one computer-readable medium, comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:

configure a programmable packet processing pipeline of a network interface device to determine, based upon transmit window overage data, a path to transmit a packet based on relative network traffic transmitted via multiple paths;

wherein:

the transmit window overage data is to indicate amounts of transmitted packet data that exceed data allocations of the multiple paths.

2. The at least one computer-readable medium of claim 1 , wherein the determine a path to transmit a packet based on relative network traffic transmitted via multiple paths is based on prior traffic amount through one or more of the multiple paths.

3. The at least one computer-readable medium of claim 1 , wherein the programmable packet processing pipeline includes:

a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes,

a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and

at least one child node is associated with the determined path.

4. The at least one computer-readable medium of claim 3 , wherein:

the first stage is to manage transmit overage for a first group of two or more child nodes,

the second stage to manage transmit overage for a second group of two or more child nodes, and

the first group includes the second group but the second group does not include all nodes of the first group.

5. The at least one computer-readable medium of claim 1 , wherein

the programmable packet processing pipeline is programmable by one or more of:

Programming Protocol-independent Packet Processors (P4), C, Python, Broadcom Network Programming Language (NPL), or an executable binary.

6. The at least one computer-readable medium of claim 1 , wherein the programmable packet processing pipeline is to maintain byte transmission count using a power of 2 tree data structure that stores packet byte overage associated with two paths, wherein one of the two paths comprises two or more child nodes.

7. The at least one computer-readable medium of claim 1 , wherein the network interface device comprises one or more of: network interface controller (NIC), SmartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), data processing unit (DPU), or Compute Express Link (CXL) switch.

8. An apparatus comprising:

a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine, based upon transmit window overage data, a path to transmit a packet based on relative network traffic transmitted via multiple paths;

wherein:

the transmit window overage data is to indicate amounts of transmitted packet data that exceed data allocations of the multiple paths.

9. The apparatus of claim 8 , wherein the determine a path to transmit a packet is based on Deficit Round Robin (DRR).

10. The apparatus of claim 8 , wherein the programmable packet processing pipeline circuitry includes:

a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes,

a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and

at least one child node is associated with the determined path.

11. The apparatus of claim 10 , wherein

the first stage is to manage transmit overage for a first group of two or more child nodes,

the second stage to manage transmit overage for a second group of two or more child nodes, and

the first group includes the second group but the second group does not include all nodes of the first group.

12. The apparatus of claim 8 , wherein

the multi-stage programmable packet processing pipeline circuitry is programmable by one or more of: Programming Protocol-independent Packet Processors (P4), C, Python, Broadcom Network Programming Language (NPL), or an executable binary.

13. The apparatus of claim 8 , wherein the relative network traffic transmitted via multiple paths is based on data structure that stores packet byte overage associated with two paths, wherein one of the two paths comprises two or more child nodes.

14. The apparatus of claim 8 , wherein the network interface device comprises one or more of: network interface controller (NIC), SmartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), data processing unit (DPU), or Compute Express Link (CXL) switch.

15. The apparatus of claim 8 , comprising a server to cause the network interface device to transmit the packet.

16. The apparatus of claim 15 , comprising a datacenter that includes the server, wherein the path comprises a port and the port is to transmit the packet to another server in the datacenter.

17. A method comprising:

determining, by a programmable packet processing pipeline, based upon transmit window overage data, a path to transmit a packet based on relative network traffic transmitted via multiple paths;

wherein:

the transmit window overage data is to indicate amounts of transmitted packet data that exceed data allocations of the multiple paths.

18. The method of claim 17 , wherein the programmable packet processing pipeline includes:

a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes,

a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and

at least one child node is associated with the determined path.

19. The method of claim 17 , comprising:

programming the programmable packet processing pipeline by one or more of:

Programming Protocol-independent Packet Processors (P4), C, Python, Broadcom Network Programming Language (NPL), or an executable binary.

20. The method of claim 17 , wherein the relative network traffic transmitted via multiple paths is based on data structure that stores packet byte overage associated with two paths, wherein one of the two paths comprises two or more child nodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2022
From: AGRAWAL, ANURAG; FINGERHUT, JOHN ANDREW; DING, XIAOYAN; ZHANG, SONG
To: INTEL CORPORATION
Reel/Frame 061828/0086 →
Continuity (1)
Related Publication 20220109639A1 · Apr 7, 2022
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