Granted Patent B2

US 12,411,784 · App. 18/155,436 · Granted Sep 9, 2025

Inventors: Yuanfen Zheng (Kirchheim, DE); Boris Alexander Niedetzky (Munich, DE); Henrik Hostalka (Dresden, DE)

Assignee: Infineon Technologies AG

G06F13/28G06F13/24

Abstract

Claims (80)

1. A direct memory access (DMA) system, comprising:

input interface circuitry configured to be coupled to a source memory, and configured to read a data packet of a sensor from the source memory, wherein the source memory is configured to receive the data packet from the sensor;

processing circuitry coupled to the input interface circuitry, the processing circuitry configured to:

receive the data packet from the input interface circuitry,

determine whether the data packet comprises a synchronized data frame, and

extract a payload of the synchronized data frame in response to a determination that the data packet comprises the synchronized data frame, wherein the payload comprises radar data, and extracting the payload includes extracting a detection bit from a header of the synchronized data frame, and the detection bit indicates detection of an object by the sensor; and

output interface circuitry coupled to the processing circuitry, the output interface circuitry configured to write the extracted payload or data derived from the extracted payload to a destination memory.

2. The DMA system of claim 1 , wherein:

the data packet comprises status data indicating a status of the sensor;

the processing circuitry is further configured to determine whether the status data indicate an error of the sensor; and

the output interface circuitry is further configured to send an interrupt command to further processing circuitry external to the DMA system in response to a determination that the status data indicates the error of the sensor.

3. The DMA system of claim 1 , wherein the processing circuitry is further configured to:

detect synchronization data in the data packet; and

determine whether the data packet comprises the synchronized data frame based on the synchronization data.

4. The DMA system of claim 3 , wherein the processing circuitry is further configured to extract the payload of the synchronized data frame based on a frame length of the synchronized data frame.

5. The DMA system of claim 4 , wherein the processing circuitry is further configured to determine the frame length based on at least one of the synchronization data or the header of the synchronized data frame.

6. The DMA system of claim 1 , wherein:

the processing circuitry is further configured to extract sensor configuration data from the header of the synchronized data frame;

the sensor configuration data indicates a configuration of the sensor; and

the output interface circuitry is further configured to write the sensor configuration data to the destination memory.

7. The DMA system of claim 1 , wherein:

the data packet comprises DMA configuration data indicating a desired configuration of the DMA system; and

the processing circuitry is further configured to configure the DMA system based on the DMA configuration data.

8. The DMA system of claim 7 , wherein the desired configuration comprises a DMA transfer mode or a network address of the source memory.

9. The DMA system of claim 8 , wherein the DMA transfer mode comprises a single mode, a block mode, or a demand mode.

10. The DMA system of claim 1 , wherein the processing circuitry is further configured to:

determine whether the data packet comprises invalid data; and

discard the invalid data in response to a determination that the data packet comprises invalid data.

11. The DMA system of claim 10 , wherein:

the data packet comprises status data indicating a status of the sensor; and

the processing circuitry is configured to:

determine whether the data packet comprises invalid data by determining whether the data packet comprises data between the status data and the synchronized data frame, and

discard the data between the status data and the synchronized data frame in response to a determination that the data packet comprises data between the status data and the synchronized data frame.

12. The DMA system of claim 10 , wherein:

the data packet comprises a second synchronized data frame following the synchronized data frame; and

wherein the processing circuitry is further configured to:

determine whether the data packet comprises invalid data by determining whether the data packet comprises data between the synchronized data frame and the second synchronized data frame, and

discard the data between the synchronized data frame and the second synchronized data frame in response to a determination that the data packet comprises data between the synchronized data frame and the second synchronized data frame.

13. The DMA system of claim 10 , wherein the processing circuitry is configured to:

determine whether the data packet comprises invalid data by determining whether the data packet comprises data preceding the synchronized data frame; and

discard the data preceding the synchronized data frame in response to a determination that the data packet comprises data preceding the synchronized data frame.

14. The DMA system of claim 10 , wherein:

the data packet comprises status data indicating a status of the sensor; and

the processing circuitry is further configured to:

determine whether the data packet comprises invalid data by determining whether the status data indicate an error of the sensor, and

discard data of the data packet following the status data in response to a determination that the status data indicates the error of the sensor.

15. A system comprising:

The DMA system of claim 1 ; and

further processing circuitry external to the DMA system, wherein the further processing circuitry is configured to perform radar processing on the extracted payload or the data derived from the extracted payload.

16. A system for processing sensor data, comprising:

a source memory configured to receive sensor data from a sensor;

a destination memory;

a direct memory access (DMA) system, comprising:

input interface circuitry coupled to the source memory, the input interface circuit configured to read a data packet of the sensor from the source memory;

processing circuitry coupled to the input interface circuitry, the processing circuitry configured to:

receive the data packet from the input interface circuitry,

determine whether the data packet comprises a synchronized data frame, and

extract a payload of the synchronized data frame in response to a determination that the data packet comprises the synchronized data frame, wherein the payload comprises radar data, extracting the payload includes extracting a detection bit from a header of the synchronized data frame, and the detection bit indicates detection of an object by the sensor; and

output interface circuitry coupled to the processing circuitry, the output interface circuitry configured to write the extracted payload or data derived from the extracted payload to the destination memory; and

further processing circuitry external to the DMA system and coupled to the destination memory, the further processing circuitry configured to:

read the extracted payload or the data derived from the extracted payload from the destination memory, and

process the extracted payload or the data derived from the extracted payload by performing radar processing on the extracted payload or the data derived from the extracted payload.

17. The system of claim 16 , wherein the processing circuitry of the DMA system is configured to extract the payload from the data packet without involvement of the further processing circuitry.

18. The system of claim 16 , further comprising a sensor interface configured to receive the data packet from the sensor via a synchronous serial communication bus, wherein the source memory is coupled to the sensor interface and configured to receive the data packet from the sensor interface.

19. A method, comprising:

receiving, by a source memory, a data packet of a sensor;

reading, by a direct memory access (DMA) system, the data packet from the source memory;

determining, by the DMA system, whether the data packet comprises a synchronized data frame;

extracting, by the DMA system, a payload of the synchronized data frame in response to a determination that the data packet comprises the synchronized data frame, wherein the payload comprises radar data, extracting the payload includes extracting a detection bit from a header of the synchronized data frame, and the detection bit indicates detection of an object by the sensor;

writing, by the DMA system, the extracted payload or data derived from the extracted payload to a destination memory; and

performing, by a processor external to the DMA system, radar processing on the extracted payload.

20. The method of claim 19 , wherein:

the data packet comprises status data indicating a status of the sensor; and

the method further comprises:

determining whether the status data indicate an error of the sensor; and

sending an interrupt command to further processing circuitry external to the DMA system in response to a determination that the status data indicates the error of the sensor.

21. The method of claim 19 , further comprising:

detecting synchronization data in the data packet; and

determining whether the data packet comprises the synchronized data frame based on the synchronization data.

22. The method of claim 21 , further comprising extracting the payload of the synchronized data frame based on a frame length of the synchronized data frame.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (32)