Duty compensation scheme
View Patent ↗A global clock signal distribution system includes a distribution line that includes gates for signal distribution, a function block gate with at least two input ports and a duty compensation gate with at least two input ports. The duty compensation gate is inserted in the distribution line following the function block gate for balancing rise-to-fall delay and fall-to-rise delay. The duty compensation gate delays an earlier arrived edge of the clock signal more than a later arrived edge of the clock signal to compensate delay unbalance.
1. A global clock signal distribution system, comprising:
a distribution line that includes gates for signal distribution;
a function block gate with at least two input ports; and
a duty compensation gate with at least two input ports, wherein the duty compensation gate is inserted in the distribution line following the function block gate for balancing rise-to-fall delay and fall-to-rise delay, the duty compensation gate delays an earlier arrived edge of a clock signal more than a later arrived edge of the clock signal to compensate delay unbalance.
2. The global clock signal distribution system of claim 1 , wherein the gates for signal distribution include inverter gates or buffer gates.
3. The global clock signal distribution system of claim 1 , wherein the function block gate with multiple input ports is configured for clock gating.
4. The global clock signal distribution system of claim 1 , wherein the function block gate with multiple input ports is configured for clock switching.
5. The global clock signal distribution system of claim 1 , wherein the function block gate and the duty compensation gate have a same structure.
6. The global clock signal distribution system of claim 1 , wherein the duty compensation gate receives a clock signal before duty compensation to a first input port and a constant high signal to a second input port.
7. The global clock signal distribution system of claim 1 , wherein the duty compensation gate is positioned proximate to the function block gate to have a same electrical performance.
8. The global clock signal distribution system of claim 1 , wherein an equal number of function block gates and duty compensation gates are placed in the distribution line to select one clock signal out of multiple input clock signals.
9. A global clock signal distribution system comprising:
a distribution line that includes gates for signal distribution;
a function block gate; and
a duty compensation gate having a same structure as the function block gate, the duty compensation gate being positioned in the distribution line following the function block gate to balance rise-to-fall delay and fall-to-rise delay within the distribution line, where the duty compensation gate delays an earlier arrived edge of a clock signal more than a later arrived edge of the clock signal to compensate delay unbalance.
10. The global clock signal distribution system of claim 9 , wherein the gates for signal distribution include inverter gates or buffer gates.
11. The global clock signal distribution system of claim 9 , wherein the function block gate is configured for clock-gating.
12. The global clock signal distribution system of claim 9 , wherein the function block gate is configured for clock-switching.
13. The global clock signal distribution system of claim 9 , wherein the function block gate and the duty compensation gate have a same electrical performance.
14. The global clock signal distribution system of claim 9 , wherein the duty compensation gate receives a clock signal at a first input port and a second input port is set to high.
15. The global clock signal distribution system of claim 9 , wherein the duty compensation gate is placed close to a corresponding function block gate to have a same electrical performance.
16. The global clock signal distribution system of claim 9 , wherein an equal number of function block gates and duty compensation gates are placed in the distribution line to select one clock signal out of multiple input clock signals.
17. A global clock signal distribution method comprising:
configuring a distribution line with gates for signal distribution and a function block gate with at least two input ports; and
positioning a duty compensation gate with at least two input ports in the distribution line following the function block gate, wherein the duty compensation gate balances rise-to-fall delay and fall-to-rise delay and the duty compensation gate delays an earlier arrived edge of a clock signal more than a later arrived edge of the clock signal to compensate delay unbalance.
18. The method of claim 17 , wherein the function block gate with multiple input ports is configured for clock gating or clock switching.
19. The method of claim 17 , wherein the function block gate and the duty compensation gate have a same electrical performance.
20. The method of claim 17 , wherein the duty compensation gate receives a clock signal to a first input port and includes a second input port set to high, wherein the duty compensation gate is placed as close to a corresponding function block gate as possible to have a same electrical performance.