Switch-managed resource allocation and software execution
Examples described herein relate to a switch device for a rack of two or more physical servers, wherein the switch device is coupled to the two or more physical servers and the switch device performs packet protocol processing termination for received packets and provides payload data from the received packets without a received packet header to a destination buffer of a destination physical server in the rack. In some examples, the switch device comprises at least one central processing unit, the at least one central processing unit is to execute packet processing operations on the received packets. In some examples, a physical server executes at least one virtualized execution environments (VEE) and the at least one central processing unit executes a VEE for packet processing of packets with data to be accessed by the physical server that executes the VEE.
1. A packaged integrated circuit, the packaged integrated circuit being configurable to be used in switching operations in association with at least one network, multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the packaged integrated circuit comprising:
interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs; and
switch circuitry to implement the switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition;
the switching operations and/or the respective communication processing are software programmable, at least in part; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.
2. The packaged integrated circuit of claim 1 , wherein:
the packaged integrated circuit comprises a system-on-chip.
3. The packaged integrated circuit of claim 2 , wherein:
the packaged integrated circuit is to implement control plane/management processes in association with the switching operations and/or the respective data communication processing.
4. The packaged integrated circuit of claim 3 , wherein:
the packaged integrated circuit is to implement congestion control and load balancing in association with the switching operations and/or the respective data communication processing.
5. The packaged integrated circuit of claim 4 , wherein:
the GPUs are configurable to implement operations associated with artificial intelligence and/or machine learning models.
6. The packaged integrated circuit of claim 5 , wherein:
the packaged integrated circuit is to be comprised in a multi-switch network.
7. The packaged integrated circuit of claim 6 , wherein:
the packaged integrated circuit comprises an application specific integrated circuit.
8. A method implemented using a packaged integrated circuit, the packaged integrated circuit being configurable to be used in switching operations in association with at least one network, multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the packaged integrated circuit comprising interface circuitry and switch circuitry, the interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs, the method comprising:
implementing, using the switch circuitry, switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.
9. The method of claim 8 , wherein:
the packaged integrated circuit comprises a system-on-chip.
10. The method of claim 9 , wherein:
the packaged integrated circuit is to implement control plane/management processes in association with the switching operations and/or the respective data communication processing.
11. The method of claim 10 , wherein:
the packaged integrated circuit is to implement congestion control and load balancing in association with the switching operations and/or the respective data communication processing.
12. The method of claim 11 , wherein:
the GPUs are configurable to implement operations associated with artificial intelligence and/or machine learning models.
13. The method of claim 12 , wherein:
the packaged integrated circuit is to be comprised in a multi-switch network.
14. The method of claim 13 , wherein:
the packaged integrated circuit comprises an application specific integrated circuit.
15. At least one non-transitory machine-readable storage medium storing instructions to be executed by a packaged integrated circuit, the packaged integrated circuit being configurable to be used in switching operations in association with at least one network, multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the packaged integrated circuit comprising interface circuitry and switch circuitry, the interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs, the instructions, when executed by the packaged integrated circuit, resulting in performance of operations comprising:
implementing, using the switch circuitry, switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition;
the switching operations and/or the respective data communication processing are software programmable, at least in part; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.
16. The at least one non-transitory machine-readable storage medium of claim 15 , wherein:
the packaged integrated circuit comprises a system-on-chip.
17. The at least one non-transitory machine-readable storage medium of claim 16 , wherein:
the packaged integrated circuit is to implement control plane/management processes in association with the switching operations and/or the respective data communication processing.
18. The at least one non-transitory machine-readable storage medium of claim 17 , wherein:
the packaged integrated circuit is to implement congestion control and load balancing in association with the switching operations and/or the respective data communication processing.
19. The at least one non-transitory machine-readable storage medium of claim 18 , wherein:
the GPUs are configurable to implement operations associated with artificial intelligence and/or machine learning models.
20. The at least one non-transitory machine-readable storage medium of claim 19 , wherein:
the packaged integrated circuit is to be comprised in a multi-switch network.
21. The at least one non-transitory machine-readable storage medium of claim 20 , wherein:
the packaged integrated circuit comprises an application specific integrated circuit.
22. A server system for use in association with at least one network, multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the server system comprising:
a packaged integrated circuit, the packaged integrated circuit to be used in switching operations in association with the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs, the packaged integrated circuit comprising:
interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs; and
switch circuitry to implement the switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition;
the switching operations and/or the respective data communication processing are software programmable, at least in part; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.
23. The server system of claim 22 , wherein:
the packaged integrated circuit comprises a system-on-chip.
24. The server system of claim 23 , wherein:
the packaged integrated circuit is to implement control plane/management processes in association with the switching operations and/or the respective data communication processing.
25. The server system of claim 24 , wherein:
the packaged integrated circuit is to implement congestion control and load balancing in association with the switching operations and/or the respective data communication processing.
26. The server system of claim 25 , wherein:
the GPUs are configurable to implement operations associated with artificial intelligence and/or machine learning models.
27. The server system of claim 26 , wherein:
the packaged integrated circuit is to be comprised in a multi-switch network.
28. The server system of claim 27 , wherein:
the packaged integrated circuit comprises an application specific integrated circuit.
29. A data center system for use in association with at least one network, the data center system comprising:
one or more server systems comprising multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the one or more server systems also comprising a packaged integrated circuit, the packaged integrated circuit to be used in switching operations in association with the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs, the packaged integrated circuit comprising:
interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs; and
switch circuitry to implement the switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition;
the switching operations and/or the respective data communication processing are software programmable, at least in part; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.
30. The data center system of claim 29 , wherein:
the one or more server systems comprise multiple server systems; and
the packaged integrated circuit comprises a system-on-chip.
31. The data center system of claim 30 , wherein:
the packaged integrated circuit is to implement control plane/management processes in association with the switching operations and/or the respective data communication processing.
32. The data center system of claim 31 , wherein:
the packaged integrated circuit is to implement congestion control and load balancing in association with the switching operations and/or the respective data communication processing.
33. The data center system of claim 32 , wherein:
the GPUs are configurable to implement operations associated with artificial intelligence and/or machine learning models.
34. The data center system of claim 33 , wherein:
the packaged integrated circuit is to be comprised in a multi-switch network.
35. The data center system of claim 34 , wherein:
the packaged integrated circuit comprises an application specific integrated circuit.