Digital twin framework for next generation networks
A digital twin model is generated for physical nodes of an edge network. The digital twin model includes a digital twin for a physical node of the physical nodes. An error is identified of the physical node or the digital twin for the physical node. The digital twin model is updated to halt communication with the physical node or the digital twin of the physical node. A path is created to another physical node or a digital twin of the another physical node in the digital twin model.
1. A system for a digital twin framework for an edge network comprising:
at least one processor; and
memory including instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
generate a digital twin model for physical nodes in the edge network, wherein the digital twin model includes a digital twin for a physical node of the physical nodes, the digital twin replicating the physical node;
establish a coalition that includes peer physical nodes, digital twins of the peer physical nodes, and the physical node or the digital twin for the physical node;
receive output metrics from members of the coalition; and
determine that output metrics from the physical node or the digital twin for the physical node are inconsistent with output metrics from the peer physical nodes and digital twins;
identify an error of the physical node or the digital twin for the physical node based in part on the inconsistency;
update the digital twin model to halt communication with the physical node or the digital twin of the physical node; and
create a path to another physical node or a digital twin of the another physical node in the digital twin model.
2. The system of claim 1 , wherein the physical nodes are discovered by a wireless broadcast messaging-based handshake protocol.
3. The system of claim 1 , the memory further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to periodically update the digital twin model based on position, features, or trajectory of the physical node or the digital twin of the physical node.
4. The system of claim 1 , wherein the error is identified by an edge computing node, a second physical node, or a digital twin of the second physical node.
5. The system of claim 1 , wherein the error is identified based in part on receipt of degraded data from the physical node or the digital twin for the physical node, failure to receive data from the physical node or the digital twin for the physical node, or receipt of erroneous data from the physical node or the digital twin for the physical node.
6. The system of claim 1 , wherein the digital twin model includes synchronization paths between the physical node and the digital twin replicating the physical node and between the digital twin replicating the physical node and another digital twin of the physical node.
7. The system of claim 1 , wherein the instructions to generate the digital twin model further comprises instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
transmit an attestation request to the physical nodes;
receive attestation results from the physical nodes;
create a digital twin corresponding to each physical node of the physical nodes based on the attestation results;
transmit the attestation request to digital twin for each physical node of the physical nodes;
receive attestation results from the digital twin for each physical node of the physical nodes; and
add the physical nodes and the digital twin for each physical node of the physical nodes to the digital twin model based on the attestation results from the physical nodes and the attestation results from the digital twin for each physical node of the physical nodes.
8. The system of claim 7 , wherein the attestation request is transmitted by a physical node of the physical nodes or a digital twin of the digital twin for each physical node.
9. The system of claim 7 , the memory further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
create an attestation appraisal policy that includes an equivalency attestation policy;
receive a unique identifier and a class identifier in an attestation result from a digital twin of the digital twin;
determine that an attestation policy using the unique identifier leads to an attestation failure;
select the equivalency attestation policy based on the class identifier; and
perform attestation of the digital twin using the equivalency attestation policy.
10. The system of claim 9 , the memory further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
generate an environment model for the class identifier, the environment model including attestation components available to nodes of a class and dependencies of nodes of the class; and
generate the equivalency attestation policy using the environment model.
11. The system of claim 9 , wherein the equivalency attestation policy includes security equivalencies that define equivalent security attestation features and environment equivalencies that define equivalent environmental attestation features.
12. The system of claim 1 , the memory further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
upon detection of the error, perform attestation of the physical node or the digital twin for the physical node using a root-of-trust;
set read and write latches in memory during performance of the attestation;
transfer execution of a workload to another physical node or another digital twin, wherein the digital twin model is updated with the another physical node or another digital twin; and
remove the read and write latches.
13. The system of claim 1 , the memory further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to discover the physical nodes in the edge network.
14. At least one non-transitory machine-readable memory including instructions for a digital twin framework for an edge network that, when executed by at least one processor, cause the at least one processor to perform operations to:
generate a digital twin model for physical nodes in the edge network, wherein the digital twin model includes a digital twin for a physical node of the physical nodes, the digital twin replicating the physical node;
establish a coalition that includes peer physical nodes, digital twins of the peer physical nodes, and the physical node or the digital twin for the physical node;
receive output metrics from members of the coalition; and
determine that output metrics from the physical node or the digital twin for the physical node are inconsistent with output metrics from the peer physical nodes and digital twins;
identify an error of the physical node or the digital twin for the physical node based in part on the inconsistency;
update the digital twin model to halt communication with the physical node or the digital twin of the physical node; and
create a path to another physical node or a digital twin of the another physical node in the digital twin model.
15. The at least one non-transitory machine-readable memory of claim 14 , wherein the physical nodes are discovered by a wireless broadcast messaging-based handshake protocol.
16. The at least one non-transitory machine-readable memory of claim 14 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to periodically update the digital twin model based on position, features, or trajectory of the physical node or the digital twin of the physical node.
17. The at least one non-transitory machine-readable memory of claim 14 , wherein the error is identified by an edge computing node, a second physical node, or a digital twin of the second physical node.
18. The at least one non-transitory machine-readable memory of claim 14 , wherein the error is identified in part based on receipt of degraded data from the physical node or the digital twin for the physical node, failure to receive data from the physical node or the digital twin for the physical node, or receipt of erroneous data from the physical node or the digital twin for the physical node.
19. The at least one non-transitory machine-readable memory of claim 14 , wherein the digital twin model includes synchronization paths between the physical node and the digital twin replicating the physical node and between the digital twin replicating the physical node and another digital twin of the physical node.
20. The at least one non-transitory machine-readable memory of claim 14 , wherein the instructions to generate the digital twin model further comprises instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
transmit an attestation request to the physical nodes;
receive attestation results from the physical nodes;
create a digital twin corresponding to each physical node of the physical nodes based on the attestation results;
transmit the attestation request to the digital twin for each physical node of the physical nodes;
receive attestation results from the digital twin for each physical node of the physical nodes; and
add the physical nodes and the digital twin for each physical node of the physical nodes to the digital twin model based on the attestation results from the physical nodes and the attestation results from the digital twin for each physical node of the physical nodes.
21. The at least one non-transitory machine-readable memory of claim 20 , wherein the attestation request is transmitted by a physical node of the physical nodes or a digital twin of the digital twin for each physical node.
22. The at least one non-transitory machine-readable memory of claim 20 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
create an attestation appraisal policy that includes an equivalency attestation policy;
receive a unique identifier and a class identifier in an attestation result from a digital twin of the digital twin;
determine that an attestation policy using the unique identifier leads to an attestation failure;
select the equivalency attestation policy based on the class identifier; and
perform attestation of the digital twin using the equivalency attestation policy.
23. The at least one non-transitory machine-readable memory of claim 22 , further comprising instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
generate an environment model for the class identifier, the environment model including attestation components available to nodes of a class and dependencies of nodes of the class; and
generate the equivalency attestation policy using the environment model.