Power management for a graphics processing unit or other circuit
In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.
1. An integrated circuit comprising:
a processor;
power monitor circuitry coupled to the processor and configured to generate a power measurement representing power consumed in the processor; and
controller circuitry coupled to the power monitor circuitry and the processor and configured to implement a feedback loop to perform the following procedure multiple times:
generate a target power measurement based on an amount of remaining battery life in a battery that is a source of power to the integrated circuit;
determine an error between the target power measurement and a power measurement generated by the power monitor circuitry;
based on the determined error:
select a limit for a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount such that the processor is powered off during a remainder of the fixed time period beyond the limit, wherein the controller circuitry is configured to determine the limit amount at a current powered first operating point of the processor having a first non-zero frequency and a first non-zero supply voltage; and
alter a subsequent powered operating point of the processor to a powered second operating point, having a second non-zero frequency and a second non-zero supply voltage, including to select the second operating point based on a non-zero length of the first amount of time.
2. The integrated circuit as recited in claim 1 , wherein the controller circuitry is configured to generate the target power measurement further based on a desired amount of time that remaining power in the battery is to last.
3. The integrated circuit as recited in claim 1 wherein the controller circuitry is configured to:
detect that the first amount of time is less than a first threshold; and
reduce the subsequent operating point based on detecting that the first amount of time is less than the first threshold.
4. The integrated circuit as recited in claim 3 wherein the controller circuitry is configured to:
detect that the first amount of time is greater than a second threshold and that the first limit amount is at a maximum; and
increase the subsequent operating point based on detecting that the first amount of time is greater than the second threshold and that the first limit amount is at the maximum.
5. The integrated circuit as recited in claim 1 wherein the controller circuitry comprises a second processor and a non-transitory computer accessible storage medium storing a plurality of instructions which, when executed by the second processor, causes the second processor to perform operations comprising at least a portion of operations performed by the controller circuitry during use.
6. The integrated circuit as recited in claim 5 wherein the controller circuitry further comprises hardware circuitry configured to perform a remaining portion of operations performed by the controller circuitry during use.
7. The integrated circuit as recited in claim 1 wherein the controller circuitry is configured to power off the processor in the given fixed time period based on completion of a task even if the first limit amount has not been exhausted.
8. The integrated circuit as recited in claim 1 wherein the power monitor circuitry is configured to estimate the power measurement based on activity in the processor.
9. The integrated circuit as recited in claim 1 wherein the power monitor circuitry is configured to measure power consumption from a power supply to the processor to determine the power measurement.
10. The integrated circuit as recited in claim 1 wherein the given fixed time period is one of a plurality of fixed time periods over which the processor operates, and wherein the processor performs a task within each of the plurality of fixed time periods during use, and wherein the controller circuitry is configured to permit the processor to exceed the first limit amount subsequent to one or more of the plurality of fixed time periods in which the processor completed the task in less than the first limit amount.
11. A method comprising:
performing, by a computing system, the following procedure multiple times in a feedback loop:
generating a power measurement representing power consumed in a processor;
generating a target power measurement based on an amount of remaining battery life in a battery that is a source of power to the processor;
determining an error between the target power measurement and the power measurement; and
based on the determined error:
selecting a limit for a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount such that the processor is powered off during a remainder of the fixed time period beyond the limit, wherein the first limit amount is determined at a current powered operating point of the processor having a first non-zero frequency and a first non-zero supply voltage; and
alter a subsequent powered operating point of the processor to a powered second operating point, having a second non-zero frequency and a second non-zero supply voltage, including to select the second operating point based on a non-zero length of the first amount of time.
12. The method as recited in claim 11 wherein the generating the target power measurement is further based on a desired amount of time that remaining power in the battery is to last.
13. The method as recited in claim 11 further comprising:
detecting that the first amount of time is less than a first threshold; and
reducing the subsequent operating point based on detecting that the first amount of time is less than the first threshold.
14. The method as recited in claim 13 further comprising:
detecting that the first amount of time is greater than a second threshold and that the first limit amount is at a maximum; and
increasing the subsequent operating point based on detecting that the first amount of time is greater than the second threshold and that the first limit amount is at the maximum.
15. The method as recited in claim 11 wherein the given fixed time period is one of a plurality of fixed time periods over which the processor operates, and the processor performs a task within each of the plurality of fixed time periods during use, and the method further comprises permitting the processor to exceed the first limit amount subsequent to one or more of the plurality of fixed time periods in which the processor completed the task in less than the first limit amount.
16. A method comprising:
generating a power measurement representing power consumed in a processor;
generating a target power measurement for the processor;
determining an error between the target power measurement and the power measurement;
limiting a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount, wherein the first limit amount is determined at a current operating point of the processor based on the determined error, the given fixed time period is one of a plurality of fixed time periods over which the processor operates, wherein the processor performs a task within each of the plurality of fixed time periods during use; and
permitting the processor to exceed the first limit amount subsequent to one or more of the plurality of fixed time periods in which the processor completed the task in less than the first limit amount.
17. The method as recited in claim 16 further comprising accumulating, by an integral controller, an amount of time not consumed by the processor in the one or more of the plurality of fixed time periods.