IP Library Granted Patent US 12,424,564
Granted Patent B2
US 12,424,564 · App. 17/679,302 · Granted Sep 23, 2025

Semiconductor device having a shielding line for signal crosstalk suppression

Inventors: Chen-Lun Ting (Taipei, TW); Tseng-Fu Lu (New Taipei, TW); Yung-Chih Yang (Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L23/552G11C5/063H01L23/5283H10B12/482H10B12/488
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,424,564
App. No.
17/679,302
Granted
Sep 23, 2025
Kind
B2
Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface, a first signal line disposed on the surface of the substrate, and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Claims (36)

1. A semiconductor device, comprising:

a substrate having a surface;

first and second conductive elements disposed in the substrate, wherein a top surface of each of the first and second conductive element is exposed from the surface of the substrate;

a first signal line disposed on the surface of the substrate and on the top surface of the first conductive element, wherein the first signal line is electrically connected with the first conductive element, wherein a width of the first signal line is greater than a width of the first conductive element, such that the first signal line is in direct contact with the surface of the substrate and the top surface of the first conductive element;

a second signal line disposed on the surface of the substrate, on the top surface of the second conductive element, and spaced apart from the first signal line, wherein the second signal line is electrically connected with the second conductive element, wherein a width of the second signal line is greater than a width of the second conductive element, such that the second signal line is in direct contact with the surface of the substrate and the top surface of the second conductive element; and

a first shielding line between the first signal line and the second signal line, wherein the first shielding line is not interconnect with any one of the first and second conductive elements;

wherein the minimum distance between the first signal line and the second signal line is equal to or less than 90 nanometers (nm).

2. The semiconductor device of claim 1 , wherein the first signal line, the second signal line, and the first shielding line are substantially parallel, wherein heights of the first signal line, the second signal line, and the first shielding line are equal.

3. The semiconductor device of claim 1 , wherein the minimum width of the first shielding line is between 10 nm and 70 nm, wherein the first shielding line serves as a dummy line.

4. The semiconductor device of claim 3 , wherein the minimum width of the first shielding line is defined by a self-aligned pitch doubling technique.

5. The semiconductor device of claim 1 , wherein the minimum distance between the first signal line and the first shielding line is between 10 nm and about 40 nm.

6. The semiconductor device of claim 5 , wherein the minimum distance between the first signal line and the first shielding line is less than the minimum width of the first shielding line.

7. The semiconductor device of claim 5 , wherein the minimum distance between the first signal line and the first shielding line is greater than the minimum width of the first shielding line.

8. The semiconductor device of claim 5 , wherein the minimum distance between the first signal line and the first shielding line is substantially equal to the minimum width of the first shielding line.

9. The semiconductor device of claim 1 , further comprising:

a second shielding line in direct contact with the surface of the substrate, wherein the first signal line is disposed between the first shielding line and the second shielding line, wherein the first shielding line is electrically connected with the second shielding line, wherein the second shielding line is not interconnect with any one of the first and second conductive elements.

10. The semiconductor device of claim 9 , further comprising:

a third shielding line in direct contact with the surface of the substrate, wherein the second signal line is disposed between the first shielding line and the third shielding line, wherein the first shielding line is electrically connected with the third shielding line, wherein the third shielding line is not interconnect with any one of the first and second conductive elements.

11. The semiconductor device of claim 10 , wherein the first shielding line, the second shielding line, and the third shielding line are substantially parallel, wherein the first, second and third shielding lines are arranged to provide an electromagnetic interference (EMI) shielding protection for the first and second signal lines.

12. The semiconductor device of claim 1 , further comprising:

a first dielectric element contacting and sealing a first side of the first signal line; and

a second dielectric element contacting and sealing a second side of the first signal line opposite to the first side, wherein the second dielectric element is positioned between the first signal line and the first shielding line.

13. The semiconductor device of claim 12 , wherein the minimum width of the first dielectric element is substantially equal to the minimum width of the second dielectric element, wherein a distance between the first signal line and the first shielding line is equal to the minimum width of the second dielectric element.

14. The semiconductor device of claim 12 , wherein the first side and the second side of the first signal line are substantially perpendicular to the surface of the substrate, wherein the first and second dielectric elements are not interconnect with any one of the first and second conductive elements.

15. A semiconductor device, comprising:

a substrate having a surface;

first and second conductive elements disposed in the substrate, wherein a top surface of each of the first and second conductive element is exposed from the surface of the substrate;

a first signal line disposed on the surface of the substrate to electrically connect with the first conductive element, wherein the top surface of the first conductive element is entirely covered by the first signal line;

a second signal line disposed on the surface of the substrate to electrically connect with the second conductive element and spaced apart from the first signal line, wherein the top surface of the second conductive element is entirely covered by the second signal line; and

a first shielding line between the first signal line and the second signal line, wherein the first shielding line is not interconnect with the first and second conductive elements;

wherein the minimum distance between the first signal line and the first shielding line is equal to or less than 40 nm.

16. The semiconductor device of claim 15 , wherein the first signal line, the second signal line, and the first shielding line are substantially parallel.

17. The semiconductor device of claim 15 , wherein the minimum width of the first shielding line is between 10 nm and 70 nm.

18. The semiconductor device of claim 17 , wherein the minimum distance between the first signal line and the first shielding line is less than the minimum width of the first shielding line.

19. The semiconductor device of claim 17 , wherein the minimum distance between the first signal line and the first shielding line is greater than the minimum width of the first shielding line.

20. The semiconductor device of claim 17 , wherein the minimum distance between the first signal line and the first shielding line is substantially equal to the minimum width of the first shielding line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2022
From: TING, CHEN-LUN; LU, TSENG-FU; YANG, YUNG-CHIH
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 059088/0414 →
Continuity (1)
Related Publication 20230268287A1 · Aug 24, 2023
References Cited (28)
US 5136358A · Sakai et al. · 1992 [cited by applicant]
US 7923809B2 · Onda et al. · 2011 [cited by applicant]
US 10088950B2 · Hashimoto · 2018 [cited by applicant]
US 20060166440A1 · Kaneoka et al. · 2006 [cited by applicant]
US 20120104569A1 · Chen · 2012 [cited by applicant]
US 20120155195A1 · Carlson · 2012 [cited by examiner]
US 20140017889A1 · Lee · 2014 [cited by examiner]
US 20140096101A1 · Kitaura · 2014 [cited by applicant]
US 20140146507A1 · Lee · 2014 [cited by examiner]
US 20150177310A1 · Roehner et al. · 2015 [cited by applicant]
US 20180174894A1 · Bouche et al. · 2018 [cited by applicant]
US 20200006082A1 · Su · 2020 [cited by applicant]
US 20210125836A1 · Huang et al. · 2021 [cited by applicant]
US 20210249416A1 · Li et al. · 2021 [cited by applicant]
US 20210272806A1 · Topaloglu et al. · 2021 [cited by applicant]
US 20230136674A1 · Chen et al. · 2023 [cited by applicant]
TW 201912841A · 2019 [cited by applicant]
TW 201913762A · 2019 [cited by applicant]
TW 202002076A · 2020 [cited by applicant]
Merriam Webster OnLine Entry for Spacedly. No Date. [cited by examiner]
Oxford English Dictionary Entry for Spacedly. No Date. [cited by examiner]
American Heritage Dictionary Entry for Spacedly. No Date. [cited by examiner]
Office Action dated Jan. 7, 20232 related to Taiwanese Application No. 111121881. [cited by applicant]
Notice of Allowance dated Oct. 12, 2022 related to Taiwanese Application No. 111121879. [cited by applicant]
Summary translation of Notice of Allowance dated Oct. 12, 2022 related to Taiwanese Application No. 111121879. [cited by applicant]
Office Action and and the search report mailed on Mar. 17, 2025 related to U.S. Appl. No. 17/679,482. [cited by applicant]
Office Action and and the search report mailed on May 6, 2025 related to U.S. Appl. No. 17/679,482. [cited by applicant]
Office Action and and the search report mailed on Aug. 14, 2024 related to U.S. Appl. No. 17/679,482. [cited by applicant]