IP Library › Granted Patent US 12,425,032
Granted Patent B1
US 12,425,032 · App. 18/475,676 · Granted Sep 23, 2025

Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

Inventors: Prakash Kumar Lenka (Orissa, IN); Sumit Gupta (Madhya Pradesh, IN); Vinod Kumar (Uttar Pradesh, IN); Jitendra Kumar Yadav (Bhopal, IN); Virvasav Sinha (Bengaluru, IN); Rajashekhar Krishnamurthy Rao (Bangalore, IN)
Assignee: Cadence Design Systems Inc.
H03L7/0995H03L7/0891
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Quick Facts
Patent No.
US 12,425,032
App. No.
18/475,676
Granted
Sep 23, 2025
Kind
B1
Abstract

Embodiments included herein are directed towards a ring voltage-controlled oscillator based phase locked loop circuit. Embodiments may include an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit. Embodiments may further include a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

Claims (32)

1. A ring voltage-controlled oscillator based phase locked loop circuit comprising:

an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations;

a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit, wherein the source degeneration circuit includes a programmable resistor; and

a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

2. The ring voltage-controlled oscillator based phase locked loop circuit of claim 1 , wherein the proportional path further includes a second source degeneration circuit.

3. The ring voltage-controlled oscillator based phase locked loop circuit of claim 1 , further comprising:

first charge pump circuitry associated with the integral path.

4. The ring voltage-controlled oscillator based phase locked loop circuit of claim 1 , further comprising:

second charge pump circuitry associated with the proportional path.

5. The ring voltage-controlled oscillator based phase locked loop circuit of claim 1 , wherein the source degeneration circuit includes a MOSFET.

6. The ring voltage-controlled oscillator based phase locked loop circuit claim 1 , wherein the source degeneration circuit includes a capacitor.

7. A ring voltage-controlled oscillator based phase locked loop method comprising:

providing an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit, wherein the source degeneration circuit includes a programmable resistor; and

electrically connecting a decoupling capacitor located at a ring voltage-controlled oscillator node with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

8. The ring voltage-controlled oscillator based phase locked loop method of claim 7 , wherein the proportional path further includes a second source degeneration circuit.

9. The ring voltage-controlled oscillator based phase locked loop method of claim 7 , further comprising:

first charge pump circuitry associated with the integral path.

10. The ring voltage-controlled oscillator based phase locked loop method of claim 7 , further comprising:

second charge pump circuitry associated with the proportional path.

11. The ring voltage-controlled oscillator based phase locked loop method of claim 7 , wherein the source degeneration circuit includes a MOSFET.

12. The ring voltage-controlled oscillator based phase locked loop method of claim 7 , wherein the source degeneration circuit includes a capacitor.

13. A ring voltage-controlled oscillator based phase locked loop circuit comprising:

an integral path including a first resistor directly connected with a first transistor and a second resistor directly connected with a second transistor;

a proportional path in electrical communication with the integral path, the proportional path including a first source degeneration circuit directly connected with a first transistor and a second source degeneration circuit directly connected with a second transistor; and

a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

14. The ring voltage-controlled oscillator based phase locked loop circuit of claim 13 , further comprising:

first charge pump circuitry associated with the integral path.

15. The ring voltage-controlled oscillator based phase locked loop circuit of claim 13 , further comprising:

second charge pump circuitry associated with the proportional path.

16. The ring voltage-controlled oscillator based phase locked loop circuit of claim 13 , wherein the source degeneration circuit includes a programmable resistor.

17. The ring voltage-controlled oscillator based phase locked loop circuit of claim 13 , wherein the source degeneration circuit includes a MOSFET.

18. The ring voltage-controlled oscillator based phase locked loop circuit of claim 13 , wherein the source degeneration circuit includes a capacitor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2023
From: LENKA, PRAKASH KUMAR; GUPTA, SUMIT; KUMAR, VINOD; YADAV, JITENDRA KUMAR; SINHA, VIRVASAV; RAO, RAJASHEKHAR KRISHNAMURTHY
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 065049/0862 →
References Cited (3)
US 9178551B2 · Vigraham · 2015 [cited by examiner]
US 10361706B2 · Chattopadhyay · 2019 [cited by examiner]
US 10389368B1 · Wang · 2019 [cited by examiner]