IP Library Granted Patent US 12,426,233
Granted Patent B2
US 12,426,233 · App. 17/615,059 · Granted Sep 23, 2025

Semiconductor device and manufacturing method thereof

Inventor: Ping-Heng Wu (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10B12/03H01L21/31111H01L21/4825H01L21/76877H10B12/09H10B63/00H10D1/692
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Quick Facts
Patent No.
US 12,426,233
App. No.
17/615,059
Granted
Sep 23, 2025
Kind
B2
Abstract

A semiconductor device includes: a substrate, and a plurality of conductors. A plurality of conductors are configured to form first electrodes of capacitor structures, and are distributed on one side of the substrate in rows and columns. Each of the conductors comprises a columnar body and a plurality of annular bumps. A part of an axial direction of the columnar body is intersected with the substrate. The annular bumps are arranged around the circumference of the columnar body, and a protruding direction of the annular bumps is parallel to the substrate. The plurality of annular bumps are distributed at intervals in the axial direction of the columnar body. Annular bumps of the conductors adjacent in row and column directions are staggered in a direction perpendicular to the substrate.

Claims (24)

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of capacitor structures, the method comprising:

providing a substrate;

forming a composite layer on the substrate, the composite layer comprising first material layers and second material layers which are alternately stacked in sequence;

forming, on the composite layer, a plurality of through vias distributed in rows and columns and running through the composite layer, the plurality of through vias comprising a plurality of first through vias and a plurality of second through vias, each of the first through vias being adjacent to the second through vias in row and column directions, each of the second through vias being adjacent to the first through vias in row and column directions;

injecting a first etching solution into the first through vias, an etching speed of the first etching solution for the first material layers being greater than that of the first etching solution for the second material layers so that annular recesses are formed on sidewalls of the first through vias in the first material layers;

injecting a second etching solution into the second through vias, an etching speed of the second etching solution for the second material layers being greater than that of the second etching solution for the first material layers so that annular recesses are formed on sidewalls of the second through vias in the second material layers;

filling a conductive material in the through vias to form conductors in the through vias, the conductors being configured to form first electrodes of the capacitor structures;

forming a third conductive layer between the substrate and the composite layer; and

patterning the third conductive layer so that the third conductive layer forms a plurality of separate connection structures, each of the connection structures being configured to electrically connect one or more conductors in the capacitor structures.

2. The method for manufacturing the semiconductor device according to claim 1 , wherein

the material for the first material layers is silicon oxide, and the material for the second material layers is silicon nitride; and

the first etching solution is hydrofluoric acid, and the second etching solution is phosphoric acid.

3. The method for manufacturing the semiconductor device according to claim 1 , after filling the conductive material in the through vias, the method further comprising:

removing the first material layers and the second material layers;

forming a first dielectric layer on the surfaces of the conductors; and

forming a first conductive layer on a side of the first dielectric layer away from the substrate, the first conductive layer covering the first dielectric layer, the first conductive layer being configured to form second electrodes of the capacitor structures.

4. The method for manufacturing the semiconductor device according to claim 1 , before forming, on the composite layer, a plurality of through vias distributed in rows and columns and running through the composite layer, the method further comprising:

doping a preset concentration of ions into the first material layers and the second material layers to adjust an etching speed for the first material layers or the second material layers.

5. The method for manufacturing the semiconductor device according to claim 1 the first through vias are firstly formed on the composite layer, and annular recesses are formed on sidewalls of the first through vias in the first material layers; and then, the second through vias running through the composite layer are formed on the composite layer; and

after forming annular recess on sidewalls of the first through vias in the first material layers and before forming, on the composite layer, the second through vias running through the composite layer, the method further comprising:

injecting a sacrificial material into the first through vias.

6. The method for manufacturing the semiconductor device according to claim 5 , the conductive material is firstly filled in the second through vias and then filled in the first through vias; and

after filling the conductive material in the second through vias, the method further comprising:

removing the sacrificial material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2021
From: WU, PING-HENG
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 058232/0803 →
Priority Claims (1)
CN 202010692526.6 · Jul 17, 2020 · national
Continuity (1)
Related Publication 20230126464A1 · Apr 27, 2023
References Cited (15)
US 5843822A · Hsia et al. · 1998 [cited by applicant]
US 6387773B1 · Engelhardt · 2002 [cited by applicant]
US 6624018B1 · Yu · 2003 [cited by examiner]
US 7126180B2 · Park · 2006 [cited by applicant]
US 7205241B2 · Park et al. · 2007 [cited by applicant]
US 7999350B2 · Lu et al. · 2011 [cited by applicant]
US 10197876B2 · Wang et al. · 2019 [cited by applicant]
US 10622363B2 · Sills · 2020 [cited by applicant]
US 10825815B2 · Tang · 2020 [cited by examiner]
US 10886195B2 · Ingerly · 2021 [cited by examiner]
US 20210288047A1 · Lee · 2021 [cited by examiner]
US 20220020711A1 · Chu · 2022 [cited by examiner]
CN 110504283A · 2019 [cited by applicant]
CN 111403601A · 2020 [cited by applicant]
International Search Report in Application No. PCT/CN2021/095566, mailed on Aug. 19, 2021. [cited by applicant]