Semiconductor structure with increased number of stacked memory dies and method of manufacturing the same
A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor device are provided. The semiconductor structure comprises: a logic die provided with a first wireless communication component; a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, the first direction being parallel to the upper surface of the logic die; and a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components. Each of the plurality of memory components includes a plurality of memory dies arrayed in the first direction. Each of the plurality of memory dies is provided with a second wireless communication component. The second wireless communication component is in wireless communication with the first wireless communication component.
1. A semiconductor structure, comprising:
a logic die provided with a first wireless communication component;
a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, wherein the first direction is parallel to the upper surface of the logic die; and
a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components,
wherein each of the plurality of memory components comprises a plurality of memory dies arrayed in the first direction, wherein each of the plurality of memory dies is provided with a second wireless communication component, wherein the second wireless communication component is in wireless communication with the first wireless communication component, and
wherein at least one of the plurality of memory dies is provided with a power supply wiring layer, wherein the power supply wiring layer extends towards the logic die along an active surface of the at least one of the plurality of memory dies;
wherein each of the memory dies is provided with a plurality of power supply signal lines, and the power supply wiring layer is electrically connected to the plurality of power supply signal lines;
an end surface of the power supply wiring layer facing towards the logic die is exposed by the at least one of the plurality of memory dies;
the at least one of the plurality of memory dies is further provided with a welding bump, wherein the welding bump is connected to the end surface; and
the logic die is provided with a power supply port, wherein the power supply port is electrically connected to the welding bump;
wherein each of the plurality of memory dies is provided with the power supply wiring layer;
wherein a plurality of welding bumps are connected to the same power supply wiring layer, and the plurality of welding bumps are arranged in a second direction and spaced apart from each other, wherein the second direction is parallel to the upper surface of the logic die and perpendicular to the first direction; and
wherein the plurality of welding bumps connected to one power supply wiring layer are misaligned, in the first direction, with the plurality of welding bumps connected to another power supply wiring layer adjacent to the one power supply wiring layer.
2. The semiconductor structure according to claim 1 , wherein in the first direction, a ratio of a thickness of the first adhesive film to a thickness of each of the plurality of memory components ranges from 1:75 to 1:95.
3. The semiconductor structure according to claim 2 , wherein the thickness of the first adhesive film in the first direction ranges from 4 μm to 6 μm.
4. The semiconductor structure according to claim 1 , wherein the first adhesive film completely covers opposite side surfaces of the any two adjacent memory components.
5. The semiconductor structure according to claim 1 , wherein the first adhesive film comprises a plurality of adhesive portions spaced apart from each other,
wherein the plurality of adhesive portions cover a portion of each of opposite side surfaces of the any two adjacent memory components.
6. The semiconductor structure according to claim 5 , wherein the plurality of adhesive portions cover edges and center portions of the opposite side surfaces of the any two adjacent memory components.
7. The semiconductor structure according to claim 1 , further comprising: a second adhesive film, wherein the second adhesive film is arranged on sides of the plurality of memory components away from the logic die or on sides of the plurality of memory components close to the logic die, the second adhesive film extends across the plurality of memory components, and the second adhesive film is adhered to the plurality of memory components.
8. The semiconductor structure according to claim 7 , wherein the second adhesive film is adhered to the first adhesive film.
9. The semiconductor structure according to claim 1 , wherein each of two memory dies arranged adjacent to two opposite sides of the first adhesive film is provided with the welding bump.
10. The semiconductor structure according to claim 1 , wherein a conductive through hole is provided in each of the plurality of memory dies;
two adjacent memory dies of the plurality of memory dies form a die set;
a bonding component is provided between the two adjacent memory dies in the same die set, wherein the bonding component is connected to the conductive through hole of each of the two adjacent memory dies to electrically connect the two adjacent memory dies with each other;
two power supply wiring layers in the same die set are arranged between the two adjacent memory dies;
each of the plurality of memory dies is provided with a first power supply signal line group and a second power supply signal line group, wherein each of the first power supply signal line group and the second power supply signal line group comprises the plurality of power supply signal lines; and
two first power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to one of the two power supply wiring layers, and two second power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to another one of the two power supply wiring layers.
11. The semiconductor structure according to claim 10 , wherein the one of the two power supply wiring layers in the same die set is a power wiring layer, and the other one of the two power supply wiring layers in the same die set is a ground wiring layer;
wherein the plurality of power supply signal lines in the first power supply signal line group are power signal lines, and the first power supply signal line group is electrically connected to the power wiring layer, and wherein the plurality of power supply signal lines in the second power supply signal line group are ground signal lines, and the second power supply signal line group is electrically connected to the ground wiring layer.
12. A semiconductor device, comprising:
a substrate;
a logic die arranged on the substrate and provided with a first wireless communication component;
a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, wherein the first direction is parallel to the upper surface of the logic die; and
a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components,
wherein each of the plurality of memory components comprises a plurality of memory dies arrayed in the first direction, each of the plurality of memory dies is provided with a second wireless communication component, wherein the second wireless communication component is in wireless communication with the first wireless communication component; and
wherein at least one of the plurality of memory dies is provided with a power supply wiring layer, wherein the power supply wiring layer extends towards the logic die along an active surface of the at least one of the plurality of memory dies;
wherein each of the memory dies is provided with a plurality of power supply signal lines, and the power supply wiring layer is electrically connected to the plurality of power supply signal lines;
an end surface of the power supply wiring layer facing towards the logic die is exposed by the at least one of the plurality of memory dies;
the at least one of the plurality of memory dies is further provided with a welding bump, wherein the welding bump is connected to the end surface; and
the logic die is provided with a power supply port, wherein the power supply port is electrically connected to the welding bump;
wherein each of the plurality of memory dies is provided with the power supply wiring layer;
wherein a plurality of welding bumps are connected to the same power supply wiring layer, and the plurality of welding bumps are arranged in a second direction and spaced apart from each other, wherein the second direction is parallel to the upper surface of the logic die and perpendicular to the first direction; and
wherein the plurality of welding bumps connected to one power supply wiring layer are misaligned, in the first direction, with the plurality of welding bumps connected to another power supply wiring layer adjacent to the one power supply wiring layer.
13. The semiconductor structure according to claim 12 , wherein a conductive through hole is provided in each of the plurality of memory dies;
two adjacent memory dies of the plurality of memory dies form a die set;
a bonding component is provided between the two adjacent memory dies in the same die set, wherein the bonding component is connected to the conductive through hole of each of the two adjacent memory dies to electrically connect the two adjacent memory dies with each other;
two power supply wiring layers in the same die set are arranged between the two adjacent memory dies;
each of the plurality of memory dies is provided with a first power supply signal line group and a second power supply signal line group, wherein each of the first power supply signal line group and the second power supply signal line group comprises the plurality of power supply signal lines; and
two first power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to one of the two power supply wiring layers, and two second power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to another one of the two power supply wiring layers.
14. The semiconductor structure according to claim 13 , wherein the one of the two power supply wiring layers in the same die set is a power wiring layer, and the other one of the two power supply wiring layers in the same die set is a ground wiring layer;
wherein the plurality of power supply signal lines in the first power supply signal line group are power signal lines, and the first power supply signal line group is electrically connected to the power wiring layer, and wherein the plurality of power supply signal lines in the second power supply signal line group are ground signal lines, and the second power supply signal line group is electrically connected to the ground wiring layer.
15. A semiconductor structure, comprising:
a logic die provided with a first wireless communication component;
a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, wherein the first direction is parallel to the upper surface of the logic die; and
a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components,
wherein each of the plurality of memory components comprises a plurality of memory dies arrayed in the first direction, wherein each of the plurality of memory dies is provided with a second wireless communication component, wherein the second wireless communication component is in wireless communication with the first wireless communication component, and
wherein at least one of the plurality of memory dies is provided with a power supply wiring layer, wherein the power supply wiring layer extends towards the logic die along an active surface of the at least one of the plurality of memory dies;
wherein each of the memory dies is provided with a plurality of power supply signal lines, and the power supply wiring layer is electrically connected to the plurality of power supply signal lines;
an end surface of the power supply wiring layer facing towards the logic die is exposed by the at least one of the plurality of memory dies;
the at least one of the plurality of memory dies is further provided with a welding bump, wherein the welding bump is connected to the end surface; and
the logic die is provided with a power supply port, wherein the power supply port is electrically connected to the welding bump;
wherein each of the plurality of memory dies is provided with the power supply wiring layer;
wherein a conductive through hole is provided in each of the plurality of memory dies;
two adjacent memory dies of the plurality of memory dies form a die set;
a bonding component is provided between the two adjacent memory dies in the same die set, wherein the bonding component is connected to the conductive through hole of each of the two adjacent memory dies to electrically connect the two adjacent memory dies with each other;
two power supply wiring layers in the same die set are arranged between the two adjacent memory dies;
each of the plurality of memory dies is provided with a first power supply signal line group and a second power supply signal line group, wherein each of the first power supply signal line group and the second power supply signal line group comprises the plurality of power supply signal lines; and
two first power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to one of the two power supply wiring layers, and two second power supply signal line groups of the two adjacent memory dies in the same die set are electrically connected to another one of the two power supply wiring layers.
16. The semiconductor structure according to claim 15 , wherein the one of the two power supply wiring layers in the same die set is a power wiring layer, and the other one of the two power supply wiring layers in the same die set is a ground wiring layer;
wherein the plurality of power supply signal lines in the first power supply signal line group are power signal lines, and the first power supply signal line group is electrically connected to the power wiring layer, and wherein the plurality of power supply signal lines in the second power supply signal line group are ground signal lines, and the second power supply signal line group is electrically connected to the ground wiring layer.
17. The semiconductor structure according to claim 15 , wherein the first adhesive film completely covers opposite side surfaces of the any two adjacent memory components.
18. The semiconductor structure according to claim 15 , wherein the first adhesive film comprises a plurality of adhesive portions spaced apart from each other,
wherein the plurality of adhesive portions cover a portion of each of opposite side surfaces of the any two adjacent memory components.
19. The semiconductor structure according to claim 18 , wherein the plurality of adhesive portions cover edges and center portions of the opposite side surfaces of the any two adjacent memory components.
20. The semiconductor structure according to claim 15 , further comprising: a second adhesive film, wherein the second adhesive film is arranged on sides of the plurality of memory components away from the logic die or on sides of the plurality of memory components close to the logic die, the second adhesive film extends across the plurality of memory components, and the second adhesive film is adhered to the plurality of memory components.