High electron mobility transistor
A high electron mobility transistor includes a channel layer; a barrier layer on the channel layer and having an energy bandgap greater than an energy bandgap of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending above the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer may extend toward the gate structure.
1. A high electron mobility transistor comprising:
a channel layer;
a barrier layer on the channel layer and having an energy bandgap greater than an energy bandgap of the channel layer;
a gate structure on the barrier layer;
a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween;
a field plate electrically connected to the source electrode and extending above the gate structure; and
a field dispersion layer in contact with the barrier layer and the drain electrode, the field dispersion layer extending toward the gate structure.
2. The high electron mobility transistor of claim 1 ,
wherein a partial area of the barrier layer does not overlap the field dispersion layer.
3. The high electron mobility transistor of claim 2 ,
wherein the partial area of the barrier layer is between the gate structure and the drain electrode.
4. The high electron mobility transistor of claim 1 ,
wherein an interval between the field plate and the field dispersion layer in a widthwise direction of the channel layer is less than an interval between the gate structure and the drain electrode in the widthwise direction.
5. The high electron mobility transistor of claim 1 ,
wherein a portion of the field dispersion layer overlaps the field plate in a thickness direction of the channel layer.
6. The high electron mobility transistor of claim 1 ,
wherein a host material of the field dispersion layer comprises a same material as the barrier layer.
7. The high electron mobility transistor of claim 1 ,
wherein the field dispersion layer comprises a p-type doped semiconductor material.
8. The high electron mobility transistor of claim 1 ,
wherein the field dispersion layer comprises a plurality of first field dispersion layers arranged apart from each other in a direction crossing a widthwise direction of the channel layer.
9. The high electron mobility transistor of claim 8 ,
wherein the plurality of first field dispersion layers are arranged apart from each other in a direction perpendicular to a widthwise direction of the channel layer.
10. The high electron mobility transistor of claim 8 ,
wherein at least one of the plurality of first field dispersion layers is in contact with the drain electrode.
11. The high electron mobility transistor of claim 8 ,
wherein at least one of the plurality of first field dispersion layers is in contact with the gate structure.
12. The high electron mobility transistor of claim 8 , wherein
the field dispersion layer further comprises a second field dispersion layer,
one end of the second field dispersion layer is in contact with the plurality of first field dispersion layers, and
an other end of the second field dispersion layer is in contact with the drain electrode.
13. The high electron mobility transistor of claim 1 ,
wherein the field dispersion layer comprises a mesh structure.
14. The high electron mobility transistor of claim 1 ,
wherein a thickness of the field dispersion layer is less than a thickness of the barrier layer.
15. The high electron mobility transistor of claim 1 ,
wherein the gate structure comprises a gate electrode, a first semiconductor layer, and a second semiconductor layer that are sequentially arranged on the barrier layer.
16. The high electron mobility transistor of claim 15 ,
wherein at least one material in the first semiconductor layer is different than at least one material in the second semiconductor layer.
17. The high electron mobility transistor of claim 1 , further comprising:
an etch stop layer between the barrier layer and the gate structure, wherein
the etch stop layer is between the barrier layer and the field dispersion layer.
18. A high electron mobility transistor comprising:
a channel layer;
a barrier layer on the channel layer, the barrier layer configured to form a two-dimensional gas (2DEG) in the channel layer;
a source electrode and a drain electrode spaced apart from each other and connected to a first end of the barrier layer and a second end of the barrier layer, respectively;
a gate structure on a portion of the barrier layer between the first end of the barrier layer and the second end of the barrier layer, the gate structure being configured to form a depletion region in the 2DEG below the gate structure;
a field plate electrically connected to the source electrode and extending above the gate structure; and
a field dispersion layer on the barrier layer between the gate structure and the drain electrode, the field dispersion layer contacting the drain electrode, and the field dispersion layer including a p-type doped semiconductor material.
19. The high electron mobility transistor of claim 18 , wherein
an interval between the field plate and the field dispersion layer in a widthwise direction of the channel layer is less than an interval between the gate structure and the drain electrode in the widthwise direction, or
a portion of the field dispersion layer overlaps the field plate in a thickness direction of the channel layer.
20. The high electron mobility transistor of claim 18 , wherein
a thickness of the field dispersion layer is less than a thickness of the barrier layer.