Wire-based metallization and stringing for solar cells
Wire-based metallization and stringing techniques for solar cells, and the resulting solar cells, modules, and equipment, are described. In an example, a substrate has a surface. A plurality of N-type and P-type semiconductor regions is disposed in or above the surface of the substrate. A conductive contact structure is disposed on the plurality of N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of conductive wires, each conductive wire of the plurality of conductive wires essentially continuously bonded directly to a corresponding one of the N-type and P-type semiconductor regions.
1. A solar cell comprising:
a substrate having a surface;
a plurality of N-type and P-type semiconductor regions in or above the surface of the substrate;
a conductive contact structure on the plurality of N-type and P-type semiconductor regions, the conductive contact structure comprising a plurality of non-coated conductive wires, each non-coated conductive wire of the plurality of non-coated conductive wires bonded through a metal layer to a corresponding one of the N-type and P-type semiconductor regions, wherein each non-coated conductive wire comprises a first portion having a substantially flat surface with microgrooves extending along a longest length of the conductive wire, and each non-coated conductive wire comprises a second portion that is substantially round and has a substantially smooth surface.
2. The solar cell of claim 1 , wherein the metal layer is a metal seed layer.
3. The solar cell of claim 1 , wherein each non-coated conductive wire of the plurality of non-coated conductive wires is parallel along a direction to form a one-dimensional layout of the conductive contact structure.
4. The solar cell of claim 1 , wherein each non-coated conductive wire of the plurality of non-coated conductive wires has a flattened circular profile.
5. The solar cell of claim 1 , wherein the substrate is substantially rectangular, and wherein the plurality of N-type and P-type semiconductor regions and the plurality of non-coated conductive wires are substantially parallel to an edge of each of the substrate.