Resistive random access memory device and fabrication method thereof
A resistive memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; and a memory stack structure disposed on the conductive via and the dielectric layer. The memory stack structure includes a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer. The top electrode layer includes at least two physically separated sub-electrode portions.
1. A resistive memory device, comprising:
a substrate;
a dielectric layer disposed on the substrate;
a conductive via disposed in the dielectric layer; and
a memory stack structure disposed on the conductive via and the dielectric layer, wherein the memory stack structure comprises a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer, wherein the top electrode layer comprises at least two physically separated sub-electrode portions.
2. The resistive memory device according to claim 1 further comprising:
a dielectric wall interposed between the at least two physically separated sub-electrode portions.
3. The resistive memory device according to claim 2 , wherein the dielectric wall penetrates through an entire thickness of the top electrode layer.
4. The resistive memory device according to claim 2 , wherein the dielectric wall is in direct contact with the resistive switching layer.
5. The resistive memory device according to claim 2 , wherein the dielectric wall comprises silicon nitride.
6. The resistive memory device according to claim 2 , wherein the dielectric wall has a thickness that is greater than or equal to 10 angstroms.
7. The resistive memory device according to claim 2 further comprising:
a dielectric cap disposed on the top electrode layer and the dielectric wall.
8. The resistive memory device according to claim 7 , wherein the dielectric cap comprises silicon oxide.
9. The resistive memory device according to claim 1 further comprising:
a spacer disposed on a sidewall of the memory stack structure.
10. The resistive memory device according to claim 1 , wherein the top electrode layer comprises a titanium nitride (TiN) layer and iridium (Ir) layer, and wherein the resistive switching layer comprises a tantalum pentoxide (Ta 2 O 5 ) layer and a tantalum oxide (TaO x ) layer.
11. A method for forming a resistive memory device, comprising:
providing a substrate;
forming a dielectric layer on the substrate;
forming a conductive via in the dielectric layer; and
forming a memory stack structure on the conductive via and the dielectric layer, wherein the memory stack structure comprises a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer, wherein the top electrode layer comprises at least two physically separated sub-electrode portions.
12. The method according to claim 11 further comprising:
forming a dielectric wall between the at least two physically separated sub-electrode portions.
13. The method according to claim 12 , wherein the dielectric wall penetrates through an entire thickness of the top electrode layer.
14. The method according to claim 12 , wherein the dielectric wall is in direct contact with the resistive switching layer.
15. The method according to claim 12 , wherein the dielectric wall comprises silicon nitride.
16. The method according to claim 12 , wherein the dielectric wall has a thickness that is greater than or equal to 10 angstroms.
17. The method according to claim 12 further comprising:
forming a dielectric cap on the top electrode layer and the dielectric wall.
18. The method according to claim 17 , wherein the dielectric cap comprises silicon oxide.
19. The method according to claim 11 further comprising:
forming a spacer on a sidewall of the memory stack structure.
20. The method according to claim 11 , wherein the top electrode layer comprises a titanium nitride (TiN) layer and iridium (Ir) layer, and wherein the resistive switching layer comprises a tantalum pentoxide (Ta 2 O 5 ) layer and a tantalum oxide (TaO x ) layer.