IP Library Granted Patent US 12,430,282
Granted Patent B2
US 12,430,282 · App. 17/510,921 · Granted Sep 30, 2025

Memory system adjusting check period for remaining throughput and data processing system including the memory system

Inventors: Ji Hoon Nam (Icheon-si, KR); Eui Cheol Lim (Icheon-si, KR)
Assignee: SK hynix Inc.
G06F15/167G06F9/4843G06F9/4881G06F9/544G06F12/1072
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Quick Facts
Patent No.
US 12,430,282
App. No.
17/510,921
Granted
Sep 30, 2025
Kind
B2
Abstract

A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

Claims (30)

1. A data processing system comprising:

a first processor;

a second processor;

a memory shared by the first processor and the second processor, and

a status storage unit configured to store a remaining throughput value of a task;

wherein the first processor configured to:

instruct the second processor to process the task using the memory,

read the remaining throughput value from the status storage unit at each check timing based on a check period,

determine a check period throughput value based on a current remaining throughput value corresponding to a current check timing and a previous remaining throughput value corresponding to a previous check timing,

adjust the check period based on the current remaining throughput value and the check period throughput value, and

proceed with a subsequent task using the memory when it is determined, based on the remaining throughput value, that the second processor has completed the task.

2. The data processing system according to claim 1 , wherein the first processor sets a difference between the previous remaining throughput value and the current remaining throughput value to the check period throughput value.

3. The data processing system according to claim 1 , wherein when the current remaining throughput value exceeds a value obtained by applying a predetermined increasing rate to the check period throughput value, the first processor increases the check period by the increasing rate.

4. The data processing system according to claim 3 , wherein when the current remaining throughput value is equal to or less than the value obtained by applying the increasing rate to the check period throughput value and exceeds the check period throughput value, the first processor maintains the check period without adjusting the check period.

5. The data processing system according to claim 1 , wherein when the current remaining throughput value is equal to or less than the check period throughput value, the first processor decreases the check period by a predetermined decreasing rate.

6. The data processing system according to claim 1 , wherein the first processor starts reading the remaining throughput value by setting the check period to the initial value after the task is started.

7. The data processing system according to claim 1 , wherein the second processor stores a result of the task in a predetermined address range in the memory,

wherein the remaining throughput value is decided on the basis of a currently accessed address in the predetermined address range.

8. An operating method of a data processing system, comprising:

instructing, by a first processor, a second processor to process a task using a memory, which is shared by the first processor and the second processor;

reading, by the first processor, a remaining throughput value of the task from a status storage unit at each check timing based on a check period;

determining, by the first processor, check period throughput value based on a current remaining throughput value of a current check timing and a previous remaining throughput value of a previous check timing;

adjusting, by the first processor, the check period based on the current remaining throughput value and the check period throughput value; and

proceeding, by the first processor, with a subsequent task using the memory when it is determined, based on the remaining throughput value, that the second processor has completed the task.

9. The operating method according to claim 8 , wherein the determining of the check period throughput value comprises setting, by the first processor, a difference between the previous remaining throughput value and the current remaining throughput value to the check period throughput value.

10. The operating method according to claim 8 , wherein the adjusting of the check period comprises increasing, by the first processor, the check period by a predetermined increasing rate, when the current remaining throughput value exceeds a value obtained by applying the increasing rate to the check period throughput value.

11. The operating method according to claim 10 , wherein the adjusting of the check period comprises maintaining, by the first processor, the check period without adjusting the check period, when the current remaining throughput value is equal to or less than the value obtained by applying the increasing rate to the check period throughput value and exceeds the check period throughput value.

12. The operating method according to claim 8 , wherein the adjusting of the check period comprises decreasing, by the first processor, the check period by a predetermined decreasing rate, when the current remaining throughput value is equal to or less than the check period throughput value.

13. The operating method according to claim 8 further comprising storing, by the second processor, a result of the task in a predetermined address range in the memory,

wherein the remaining throughput value is decided based on a currently accessed address in the predetermined address range.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2021
From: NAM, JI HOON; LIM, EUI CHEOL
To: SK HYNIX INC.
Reel/Frame 057916/0804 →
Priority Claims (2)
KR 10-2018-0024836 · Feb 28, 2018 · national
KR 10-2018-0032111 · Mar 20, 2018 · national
Continuity (2)
Division 16210418 · Dec 5, 2018
Related Publication 20220058157A1 · Feb 24, 2022
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