Application programming interface to disassociate a virtual address
Apparatuses, systems, and techniques to manage memory arrays. In at least one embodiment an application programming interface (API) is performed to disassociate a virtual address indicated by the API from a corresponding physical address.
1. One or more processors, comprising:
circuitry to cause an application programming interface (API) to be performed to disassociate a virtual memory address indicated to the API from a corresponding physical storage address corresponding to a data, wherein the virtual memory address is usable to reassociate the virtual memory address to a second physical storage address corresponding to the data.
2. The one or more processors of claim 1 , wherein the virtual memory address indicated to the API is a virtual address of a non-sparse array.
3. The one or more processors of claim 1 , wherein the corresponding physical storage address is a physical storage address of backing memory of a non-sparse array.
4. The one or more processors of claim 1 , wherein the API indicates residency of data stored at the corresponding physical storage address.
5. The one or more processors of claim 1 , wherein the virtual memory address is stored in memory of a graphics processing unit.
6. The one or more processors of claim 1 , wherein the virtual memory address is stored in a page table.
7. The one or more processors of claim 1 , wherein the corresponding physical storage address is an address of a data location in memory of a graphics processing unit.
8. The one or more processors of claim 1 , wherein the circuitry is to cause a second API to be performed to associate the virtual memory address to a second corresponding physical storage address.
9. The one or more processors of claim 1 , wherein the corresponding physical storage address is a physical storage address of texture data.
10. The one or more processors of claim 1 , wherein the API indicates whether the virtual memory address is associated with the corresponding physical storage address.
11. The one or more processors of claim 1 , wherein the virtual memory address is a virtual storage address.
12. A computer-implemented method, comprising:
performing a first application programming interface (API) to disassociate a virtual memory address indicated to the first API from a first corresponding physical storage address storing data accessible using the virtual memory address; and
performing a second API to remap the virtual memory address to a second corresponding physical storage address to store the data.
13. The computer-implemented method of claim 12 , wherein the virtual memory address indicated to the first API is a virtual address of a non-sparse array.
14. The computer-implemented method of claim 12 , wherein the first corresponding physical storage address is a physical storage address of backing memory of a non-sparse array.
15. The computer-implemented method of claim 12 , wherein the first API indicates residency of data stored at the first corresponding physical storage address.
16. The computer-implemented method of claim 12 , wherein the virtual memory address is stored in memory of a graphics processing unit.
17. The computer-implemented method of claim 12 , wherein the virtual memory address is stored in memory of a parallel processing unit.
18. The computer-implemented method of claim 12 , wherein the virtual memory address is stored in memory of a general purpose graphics processing unit.
19. The computer-implemented method of claim 12 , wherein the first corresponding physical storage address is an address of a data location in memory of a graphics processing unit.
20. The computer-implemented method of claim 12 , wherein the first corresponding physical storage address is an address of a data location in host memory.
21. The computer-implemented method of claim 12 , further comprising:
retrieving an array containing one or more sentinel values as a result of reading from the virtual memory address that is disassociated from the first corresponding physical storage address.
22. The computer-implemented method of claim 12 , wherein the first corresponding physical storage address is a physical memory address.
23. A computer system comprising:
one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, cause the one or more processors to cause an application programming interface (API) to be performed to disassociate a virtual memory address indicated to the API from a corresponding physical storage address corresponding to a data, wherein the virtual memory address is usable to reassociate the virtual memory address to a second physical storage address corresponding to the data.
24. The computer system of claim 23 , wherein the virtual memory address indicated to the API is a virtual address of a non-sparse array.
25. The computer system of claim 23 , wherein the corresponding physical storage address is a physical storage address of backing memory of a non-sparse array.
26. The computer system of claim 23 , wherein the API indicates residency of data stored at the corresponding physical storage address.
27. The computer system of claim 23 , wherein the virtual memory address is stored in memory of a graphics processing unit.
28. The computer system of claim 23 , wherein the corresponding physical storage address is an address of a data location in memory of a graphics processing unit.
29. The computer system of claim 23 , wherein the API indicates that the virtual memory address is associated with the corresponding physical storage address.
30. The computer system of claim 23 , wherein the API indicates that the virtual memory address is not associated with the corresponding physical storage address.
31. The computer system of claim 23 , wherein:
the API is to receive a first parameter that includes one or more memory information structures, wherein a memory information structure of the one or more memory information structures indicates information about at least a portion of data;
the API is to receive a second parameter that indicates a count of the one or more memory information structures;
the API is to receive a third parameter that indicates an execution environment; and
the API is to return an error status indicator.
32. The computer system of claim 23 , wherein the API receives parameters including a memory handle, a map offset, and a set of map extents in a memory information parameter structure.
33. A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to cause an application programming interface (API) to be performed to disassociate a virtual memory address indicated to the API from a corresponding physical storage address corresponding to a data, wherein the virtual memory address is usable to reassociate the virtual memory address to a second physical storage address corresponding to the data.
34. The machine-readable medium of claim 33 , wherein the virtual memory address indicated by the API is a virtual address of a non-sparse array.
35. The machine-readable medium of claim 33 , wherein the corresponding physical storage address is a physical storage address of backing memory of a non-sparse array.
36. The machine-readable medium of claim 33 , wherein the API indicates residency of data stored at the corresponding physical storage address.
37. The machine-readable medium of claim 33 , wherein the virtual memory address is stored in memory of a graphics processing unit.
38. The machine-readable medium of claim 33 , wherein the corresponding physical storage address is an address of a data location in memory of a graphics processing unit.
39. The machine-readable medium of claim 33 , wherein the API indicates whether the virtual memory address is associated with the corresponding physical storage address.
40. The machine-readable medium of claim 33 , wherein the API is to receive a parameter that includes one or more memory information structures, wherein a memory information structure of the one or more memory information structures indicates information about at least a portion of data.
41. The machine-readable medium of claim 33 , wherein the API is to receive a parameter that indicates a count of one or more memory information structures.
42. The machine-readable medium of claim 33 , wherein the API is to receive a parameter that indicates an execution environment.
43. The machine-readable medium of claim 33 , wherein the API is to return an error status indicator.