Seal ring with inner setback wall for yield improvement
Display panels and methods of fabrication are described which a seal ring is formed within a build-up structure over a semiconductor substrate. The seal ring may include an outer perimeter wall and an inner setback wall spaced apart from the outer perimeter wall and directly underneath a contact ledge of the display panel.
1. A display panel comprising:
a semiconductor substrate;
a plurality of devices formed in a die area of the semiconductor substrate;
a build-up structure over the semiconductor substrate, the build-up structure including pixel wiring connected with the die area, and a seal ring laterally surrounding the pixel wiring;
an emission layer including an array of light emitting diodes (LEDs) on the build-up structure and connected with the pixel wiring; and
a cover layer over the emission layer, wherein the cover layer is not directly over a contact ledge of the build-up structure;
wherein the contact ledge spans directly over a portion of the seal ring including an outer perimeter wall adjacent a perimeter edge of the semiconductor substrate and an inner setback wall that is shifted internally from the perimeter edge relative to the outer perimeter wall.
2. The display panel of claim 1 , wherein the plurality of devices is a plurality of metal-oxide-semiconductor-field-effect-transistors (MOSFETs).
3. The display panel of claim 2 , wherein the build-up structure includes damascene interconnects.
4. The display panel of claim 3 , wherein the seal ring includes multiple stacked metal layers.
5. The display panel of claim 4 , wherein the inner setback wall is laterally spaced from the outer perimeter wall by at least 75 μm.
6. The display panel of claim 4 , wherein the inner setback wall is laterally spaced from the outer perimeter wall by 100-200 μm.
7. The display panel of claim 4 , wherein the inner setback wall is located adjacent a corner of the semiconductor substrate.
8. The display panel of claim 4 , wherein the inner setback wall includes a longitudinal length parallel to an edge of the semiconductor substrate.
9. The display panel of claim 4 , wherein the inner setback wall partially spans underneath the cover layer.
10. The display panel of claim 4 , further comprising a second inner setback wall separate from the inner setback wall.
11. The display panel of claim 4 , wherein a contour of the outer perimeter wall substantially matches a shape of the semiconductor substrate perimeter edges.
12. The display panel of claim 4 , wherein the contour of the seal ring comprises a kerf adjacent a corner of the semiconductor substrate.
13. The display panel of claim 4 , wherein the inner setback wall is contiguous with the outer perimeter wall.
14. The display panel of claim 4 , further comprising a blanket passivation layer spanning over the array of LEDs and the contact ledge, and a plurality of openings in the passivation layer exposing a plurality of contact pads on the contact ledge.
15. The display panel of claim 14 , further comprising a flex circuit bonded to the plurality of contact pads on the contact ledge.
16. The display panel of claim 15 , wherein the flex circuit is folded around a back side of the semiconductor substrate.
17. The display panel of claim 15 , further comprising a chip bonded to a portion of the plurality of contact pads on the contact ledge.
18. The display panel of claim 4 , further comprising a fiducial mark that at least partially overlaps space between the outer perimeter wall and the inner setback wall.
19. The display panel of claim 1 , wherein the inner setback wall is contiguous with the outer perimeter wall.
20. The display panel of claim 19 , wherein the seal ring is a single wall structure in which the inner setback wall is not surrounded by the outer perimeter wall.
21. The display panel of claim 19 , wherein the seal ring is a multiple wall structure in which the inner setback wall is surrounded by the outer perimeter wall.