Magnetoresistive random access memory and method for fabricating the same
A method for fabricating semiconductor device includes the step of forming a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer and the free layer includes a magnesium oxide (MgO) compound. According to an embodiment of the present invention, the free layer includes a first cap layer on the barrier layer, a spacer on the first cap layer, and a second cap layer on the spacer.
1. A method for fabricating semiconductor device, comprising:
forming a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:
a pinned layer on the substrate;
a barrier layer on the pinned layer; and
a free layer on the barrier layer, wherein the free layer comprises a magnesium oxide (MgO) compound and the free layer further comprising:
a first cap layer on the barrier layer;
a spacer on the first cap layer; and
a second cap layer on the spacer.
2. The method of claim 1 , wherein the first cap layer and the second cap layer comprise MgO.
3. The method of claim 1 , wherein the spacer comprises Mg.
4. The method of claim 1 , wherein the free layer comprises:
a cap layer on the barrier layer; and
a spacer on the cap layer.
5. The method of claim 4 , wherein the cap layer comprises MgO.
6. The method of claim 4 , wherein the spacer comprises Mg.
7. The method of claim 1 , wherein the free layer comprises a gradient oxygen concentration.
8. The method of claim 1 , wherein the free layer comprises:
a first cap layer on the barrier layer; and
a second cap layer on the first cap layer, wherein the first cap layer and the second cap layer comprise MgO.
9. The method of claim 8 , wherein the second cap layer comprises a gradient oxygen concentration.
10. A semiconductor device, comprising:
a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:
a pinned layer on the substrate;
a barrier layer on the pinned layer; and
a free layer on the barrier layer, wherein the free layer comprises a magnesium oxide (MgO) compound and the free layer further comprising:
a first cap layer on the barrier layer;
a spacer on the first cap layer; and
a second cap layer on the spacer.
11. The semiconductor device of claim 10 , wherein the first cap layer and the second cap layer comprise MgO.
12. The semiconductor device of claim 10 , wherein the spacer comprises Mg.
13. The semiconductor device of claim 10 , wherein the free layer comprises:
a cap layer on the barrier layer; and
a spacer on the first cap layer.
14. The semiconductor device of claim 13 , wherein the cap layer comprises MgO.
15. The semiconductor device of claim 13 , wherein the spacer comprises Mg.
16. The semiconductor device of claim 10 , wherein the free layer comprises a gradient oxygen concentration.
17. The semiconductor device of claim 10 , wherein the free layer comprises:
a first cap layer on the barrier layer; and
a second cap layer on the first cap layer, wherein the first cap layer and the second cap layer comprise MgO.
18. The semiconductor device of claim 17 , wherein the second cap layer comprises a gradient oxygen concentration.