Method and system for code optimization based on statistical data

1. A compiler implemented method, comprising:

receiving a high-level function in a first high-level code;

compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

generating at least one meta data during the compiling, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a layer of a machine learning (ML) model being executed on the hardware or the simulator;

transmitting the first set of low-level instructions to the hardware or the simulator;

receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions;

determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data, wherein the changes to the compilation includes at least one or more of changing a memory layout, replacing one ML library call with another ML library call, modifying a mapping of data to memory blocks, modifying a precision for an instruction, modifying quantization for the instruction, modifying a processing element to perform a particular operation associated with the instruction, reordering of data dimensions, and a change to methodology to split tensors;

recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

transmitting the second set of low-level instructions to the hardware or the simulator.

2. The compiler implemented method of claim 1 further comprising transmitting the at least one meta data to the hardware or the simulator.

3. The compiler implemented method of claim 1 , wherein the information includes a mapping of a code section of the first high-level code to the layer of the ML model.

4. The compiler implemented method of claim 1 , wherein the plurality of statistical data is automatically generated by the hardware or the simulator.

5. The compiler implemented method of claim 1 , wherein the plurality of statistical data is performance related, and wherein the plurality of statistical data includes activities associated with at least one hardware component of the hardware or the simulator during execution of the first set of low-level instructions.

6. The compiler implemented method of claim 5 , wherein the at least one hardware component includes a processing element.

7. The compiler implemented method of claim 5 , wherein the at least one hardware component includes an on-chip memory (OCM).

8. The compiler implemented method of claim 1 , wherein the statistical data is associated with a direct memory access (DMA) cycles of the hardware or the simulator.

9. The compiler implemented method of claim 1 , wherein the statistical data includes cycle counts associated with a layer of a machine learning model.

10. The compiler implemented method of claim 1 , wherein the changes to the compilation reduces at least one or more of data movement, data storage, duplication of computations, data conversions, and communications.

11. A system, comprising:

a hardware processor configured to process data; and

a compiler executing on the processor, wherein the compiler is configured to receive a high-level function in a first high-level code;

compile the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

generate at least one meta data when the high-level function is compiled into the first set of low-level instructions, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a layer of a machine learning (ML) model being executed on the hardware or the simulator;

transmit the first set of low-level instructions to the hardware or the simulator;

receive a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions;

determine whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data, wherein the changes to the compilation includes at least one or more of changing a memory layout, replacing one ML library call with another ML library call, modifying a mapping of data to memory blocks, modifying a precision for an instruction, modifying quantization for the instruction, modifying a processing element to perform a particular operation associated with the instruction, reordering of data dimensions, and a change to methodology to split tensors;

recompile the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

transmit the second set of low-level instructions to the hardware or the simulator.

12. The system of claim 11 , wherein the compiler is further configured to transmit the at least one meta data to the hardware or the simulator.

13. The system of claim 11 , wherein the information includes a mapping of a code section of the first high-level code to the layer of the ML model.

14. The system of claim 11 , wherein the plurality of statistical data is automatically generated by the hardware or the simulator.

15. The system of claim 11 , wherein the plurality of statistical data is performance related, and wherein the plurality of statistical data includes activities associated with at least one hardware component of the hardware or the simulator during execution of the first set of low-level instructions.

16. The system of claim 15 , wherein the at least one hardware component includes a processing element.

17. The system of claim 15 , wherein the at least one hardware component includes an on-chip memory (OCM).

18. The system of claim 11 , wherein the statistical data is associated with a direct memory access (DMA) cycles of the hardware or the simulator.

19. The system of claim 11 , wherein the statistical data includes cycle counts associated with a layer of a machine learning model.

20. A system, comprising:

a means for receiving a high-level function in a first high-level code;

a means for compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

a means for generate generating at least one meta data when the high-level function is compiled into the first set of low-level instructions, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a layer of a machine learning (ML) model being executed on the hardware or the simulator;

a means for transmitting the first set of low-level instructions to the hardware or the simulator;

a means for receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions;

a means for determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data, wherein the changes to the compilation includes at least one or more of changing a memory layout, replacing one ML library call with another ML library call, modifying a mapping of data to memory blocks, modifying a precision for an instruction, modifying quantization for the instruction, modifying a processing element to perform a particular operation associated with the instruction, reordering of data dimensions, and a change to methodology to split tensors;

a means for recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

a means for transmitting the second set of low-level instructions to the hardware or the simulator.

21. A compiler implemented method, comprising:

receiving a high-level function in a first high-level code;

compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

generating at least one meta data during the compiling, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a first layer of a machine learning (ML) model being executed on the hardware or the simulator, wherein the information includes a mapping of a code section of the first high-level code to the first layer of the ML model;

transmitting the first set of low-level instructions to the hardware or the simulator;

receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, and wherein the plurality of statistical data includes cycle counts associated with a second layer of the ML model;

determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data;

recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

transmitting the second set of low-level instructions to the hardware or the simulator.

22. The compiler implemented method of claim 21 further comprising transmitting the at least one meta data to the hardware or the simulator.

23. The compiler implemented method of claim 21 , wherein the plurality of statistical data is automatically generated by the hardware or the simulator, and wherein the plurality of statistical data is performance related, and wherein the plurality of statistical data includes activities associated with at least one hardware component of the hardware or the simulator during execution of the first set of low-level instructions.

24. The compiler implemented method of claim 23 , wherein the at least one hardware component includes a processing element or an on-chip memory (OCM).

25. The compiler implemented method of claim 21 , wherein the statistical data is associated with a direct memory access (DMA) cycles of the hardware or the simulator.

26. The compiler implemented method of claim 21 , wherein the changes to the compilation reduces at least one or more of data movement, data storage, duplication of computations, data conversions, and communications.

27. The compiler implemented method of claim 21 , wherein the first layer is a same as a second layer.

28. A system, comprising:

a hardware processor configured to process data; and

a compiler executing on the processor, wherein the compiler is configured to receive a high-level function in a first high-level code;

compile the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

generate at least one meta data when the high-level function is compiled into the first set of low-level instructions, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a first layer of a machine learning (ML) model being executed on the hardware or the simulator, wherein the information includes a mapping of a code section of the first high-level code to the first layer of the ML model;

transmit the first set of low-level instructions to the hardware or the simulator;

receive a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, and wherein the plurality of statistical data includes cycle counts associated with a second layer of the ML model;

determine whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data;

recompile the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

transmit the second set of low-level instructions to the hardware or the simulator.

29. The system of claim 28 , wherein the compiler is further configured to transmit the at least one meta data to the hardware or the simulator.

30. The system of claim 28 , wherein the plurality of statistical data is automatically generated by the hardware or the simulator, and wherein the plurality of statistical data is performance related, and wherein the plurality of statistical data includes activities associated with at least one hardware component of the hardware or the simulator during execution of the first set of low-level instructions.

31. The system of claim 30 , wherein the at least one hardware component includes a processing element or an on-chip memory (OCM).

32. The system of claim 28 , wherein the statistical data is associated with a direct memory access (DMA) cycles of the hardware or the simulator.

33. The system of claim 28 , wherein the first layer is a same as the second layer.

34. A system, comprising:

a means for receiving a high-level function in a first high-level code;

a means for compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator;

a means for generating at least one meta data when the high-level function is compiled into the first set of low-level instructions, wherein the at least one meta data is generated based on a strategy generated by the compiler, wherein the at least one meta data includes information associated with a first layer of a machine learning (ML) model being executed on the hardware or the simulator, wherein the information includes a mapping of a code section of the first high-level code to the first layer of the ML model;

a means for transmitting the first set of low-level instructions to the hardware or the simulator;

a means for receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, and wherein the plurality of statistical data includes cycle counts associated with a second layer of the ML model;

a means for determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data;

a means for recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and

a means for transmitting the second set of low-level instructions to the hardware or the simulator.