IP Library Granted Patent US 12,449,974
Granted Patent B2
US 12,449,974 · App. 18/784,292 · Granted Oct 21, 2025

Memory compression with improved lookup table scheme

Inventor: Su Wei Lim (Penang, MY)
Assignee: Micron Technology, Inc.
G06F3/0608G06F3/0644G06F3/0673
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Quick Facts
Patent No.
US 12,449,974
App. No.
18/784,292
Granted
Oct 21, 2025
Kind
B2
Abstract

A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

Claims (48)

1. A system comprising:

a memory; and

a processing device, operatively coupled with the memory, to perform operations comprising:

partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier;

receiving a host command to access data;

identifying a compression ratio of the data;

identifying a memory partition among the plurality of memory partitions;

identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and

performing an operation regarding the data at the identified location on the memory partition.

2. The system of claim 1 , wherein the processing device is to perform operations further comprising:

storing, in a data structure, a record indexable by a physical address specified in the host command, wherein the record includes a partition identifier of the memory partition and the segment identifier.

3. The system of claim 2 , wherein the record includes a value in the compression ratio range associated with the memory partition.

4. The system of claim 2 , wherein the processing device is to perform operations further comprising:

caching the data structure.

5. The system of claim 1 , wherein the processing device is to perform operations further comprising:

associating the compression ratio range to the memory partition.

6. The system of claim 5 , wherein identifying the memory partition among the plurality of memory partitions further comprises: determining that the compression ratio of the data falls in the compression ratio range.

7. The system of claim 1 , wherein the plurality of locations on the memory partition are determined based on the compression ratio range associated with the memory partition.

8. The system of claim 1 , wherein the memory comprises at least one of: a volatile memory device or a non-volatile memory device.

9. A method comprising:

partitioning, by a processing device, a memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier;

receiving a host command to access data;

identifying a compression ratio of the data;

identifying a memory partition among the plurality of memory partitions;

identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and

performing an operation regarding the data at the identified location on the memory partition.

10. The method of claim 9 , further comprising:

storing, in a data structure, a record indexable by a physical address specified in the host command, wherein the record includes a partition identifier of the memory partition and the segment identifier.

11. The method of claim 10 , wherein the record includes a value in the compression ratio range associated with the memory partition.

12. The method of claim 10 , further comprising:

caching the data structure.

13. The method of claim 9 , further comprising:

associating the compression ratio range to the memory partition.

14. The method of claim 13 , wherein identifying the memory partition among the plurality of memory partitions further comprises: determining that the compression ratio of the data falls in the compression ratio range.

15. The method of claim 9 , wherein the plurality of locations on the memory partition are determined based on the compression ratio range associated with the memory partition.

16. The method of claim 9 , wherein the memory comprises at least one of: a volatile memory device or a non-volatile memory device.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

partitioning a memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier;

receiving a host command to access data;

identifying a compression ratio of the data;

identifying a memory partition among the plurality of memory partitions;

identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and

performing an operation regarding the data at the identified location on the memory partition.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is to perform operations further comprising:

storing, in a data structure, a record indexable by a physical address specified in the host command, wherein the record includes a partition identifier of the memory partition and the segment identifier.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the record includes a value in the compression ratio range associated with the memory partition.

20. The non-transitory computer-readable storage medium of claim 18 , wherein the processing device is to perform operations further comprising:

caching the data structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2025
From: LIM, SU WEI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 070206/0931 →
Continuity (2)
Provisional Application 63537624 · Sep 11, 2023
Related Publication 20250085851A1 · Mar 13, 2025
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