Determining IR drop
The IR drop for a portion of a circuit may include a voltage drop across resistance, and may include a product of current I passing through resistance with a resistance value R. In order to determine IR drop for a circuit in a more accurate and efficient manner, a neural network produces coefficient maps (that each indicate a time-varying distribution of power within an associated portion of the circuit), and these coefficient maps are then used by the neural network to determine an IR drop for each of a plurality of portions of the circuit.
1. A method, comprising:
at one or more devices that implement a neural network having a convolutional neural network (CNN) layer and a regression layer, wherein the neural network is trained to predict per-cell IR drop from a plurality of given power maps for a given circuit design, and wherein the neural network is trained using a learning set of existing circuit partitions with known IR drop information, and that implement a circuit design tool:
receiving a plurality of power maps for a circuit design at the neural network;
processing the plurality of power maps, by the CNN layer of the neural network, to predict a plurality of coefficient maps that include weight factors for a plurality of cells of the circuit design;
processing the plurality of coefficient maps together with cell-level features for the plurality of cells of the circuit design, by the regression layer of the neural network, to predict an IR drop for each of the plurality of cells in the circuit design;
modifying at least one of a cell layout of the circuit design or a power distribution of the circuit design, via the circuit design tool, to improve at least one of a timing or a functionality of the circuit design, based on the IR drop predicted for each of the plurality of cells in the circuit design, wherein the modifying results in an improved circuit design; and
wherein a physical circuit is generated in accordance with the improved circuit design including at least:
placing a plurality of transistors on a circuit board in accordance with the cell layout of the improved circuit design, and
creating power distribution pathways in accordance with the power distribution of the circuit design.
2. The method of claim 1 , wherein each of the plurality of power maps includes a two-dimensional image-based representation of power dissipation within the circuit at a particular instance of time.
3. The method of claim 1 , wherein the CNN layer is a three-dimensional (3D) CNN layer.
4. The method of claim 3 , wherein the 3D CNN considers a subset of the plurality of power maps during a single iteration.
5. The method of claim 1 , wherein each of the plurality of coefficient maps indicates a time-varying distribution of power within a portion of the circuit design.
6. The method of claim 1 , wherein for each of the plurality of coefficient maps, the regression layer multiplies the coefficient map with the cell-level features to determine the IR drop for the associated cell.
7. The method of claim 1 , further comprising utilizing the CNN layer of the neural network to perform vector profiling.
8. The method of claim 7 , wherein:
vector profiling includes reducing a multi-cycle vector into a subset of cycles, and
information from the CNN layer of the neural network is used to assist in the reduction of the multi-cycle vector.
9. The method of claim 1 , wherein for each of the plurality of coefficient maps, the regression layer multiplies the weight factor included in the coefficient map for a corresponding cell of the circuit design with the cell-level features to predict the IR drop for the corresponding cell of the circuit design.
10. The method of claim 1 , wherein the cell-level features include at least one of:
internal power,
leakage power,
switching power,
toggle rate scaled power,
overlap power,
total power, or
effective distance to power rail via stacks.
11. The method of claim 1 , wherein plurality of coefficient maps include a weight factor for each cell of the circuit design.
12. The method of claim 1 , wherein the one or more devices train the neural network having the convolutional neural network (CNN) layer and the regression layer, using the learning set of existing circuit partitions with known IR drop information.
13. The method of claim 12 , wherein the learning set further includes known cell information.
14. The method of claim 1 , wherein modifying the at least one of the cell layout of the circuit design or the power distribution of the circuit design includes modifying a region of the circuit design having a threshold level of IR drop.
15. The method of claim 14 , wherein the cell layout within a region of the circuit design is modified when the region is below a threshold size and has the threshold level of IR drop.
16. The method of claim 15 , wherein the cell layout within the region of the circuit design is modified by spreading out cells in the region to reduce a cell density in the region.
17. The method of claim 14 , wherein power distribution within a region of the circuit design is modified when the region is above a threshold size and has the threshold level of IR drop.
18. The method of claim 17 , wherein the power distribution within the region of the circuit design is modified to lessen the IR drop or a concentration of the IR drop.
19. The method of claim 1 , further comprising, at the one or more devices:
generating a routing for the improved circuit design, via the circuit design tool;
wherein the physical circuit is generated by further creating wired connections among the plurality of transistors in accordance with the routing of the improved circuit design.
20. An apparatus comprising:
a non-transitory memory storage comprising instructions; and
one or more processors in communication with the memory, wherein the one or more processors execute the instructions to:
receive a plurality of power maps for a circuit design at a neural network having a convolutional neural network (CNN) layer and a regression layer, wherein the neural network is trained to predict per-cell IR drop from a plurality of given power maps for a given circuit design, and wherein the neural network is trained using a learning set of existing circuit partitions with known IR drop information;
process the plurality of power maps, by the CNN layer of the neural network, to predict a plurality of coefficient maps that include weight factors for a plurality of cells of the circuit design;
process the plurality of coefficient maps together with cell-level features for the plurality of cells of the circuit design, by the regression layer of the neural network, to predict an IR drop for each of the plurality of cells in the circuit design;
modify at least one of a cell layout of the circuit design or a power distribution of the circuit design, via the circuit design tool, to improve at least one of a timing or a functionality of the circuit design, based on the IR drop predicted for each of the plurality of cells in the circuit design, wherein the modifying results in an improved circuit design; and
wherein a physical circuit is generated in accordance with the improved circuit design including at least:
placing a plurality of transistors on a circuit board in accordance with the cell layout of the improved circuit design, and
creating power distribution pathways in accordance with the power distribution of the circuit design.
21. The apparatus of claim 20 , wherein each of the plurality of power maps includes a two-dimensional image-based representation of power dissipation within the circuit at a particular instance of time.
22. The apparatus of claim 20 , wherein the CNN layer is a three-dimensional (3D) CNN layer.
23. The apparatus of claim 22 , wherein the 3D CNN considers a subset of the plurality of power maps during a single iteration.
24. The apparatus of claim 20 , wherein each of the plurality of coefficient maps indicates a time-varying distribution of power within a portion of the circuit design.
25. A non-transitory computer-readable media storing computer instructions which when executed by one or more processors of a device cause the one or more processors to cause the device to:
receive a plurality of power maps for a circuit design at a neural network having a convolutional neural network (CNN) layer and a regression layer, wherein the neural network is trained to predict per-cell IR drop from a plurality of given power maps for a given circuit design, and wherein the neural network is trained using a learning set of existing circuit partitions with known IR drop information;
process the plurality of power maps, by the CNN layer of the neural network, to predict a plurality of coefficient maps that include weight factors for a plurality of cells of the circuit design;
process the plurality of coefficient maps together with cell-level features for the plurality of cells of the circuit design, by the regression layer of the neural network, to predict an IR drop for each of the plurality of cells in the circuit design;
modify at least one of a cell layout of the circuit design or a power distribution of the circuit design, via the circuit design tool, to improve at least one of a timing or a functionality of the circuit design, based on the IR drop predicted for each of the plurality of cells in the circuit design, wherein the modifying results in an improved circuit design; and
wherein a physical circuit is generated in accordance with the improved circuit design including at least:
placing a plurality of transistors on a circuit board in accordance with the cell layout of the improved circuit design, and
creating power distribution pathways in accordance with the power distribution of the circuit design.
26. The non-transitory computer-readable media of claim 25 , wherein each of the plurality of power maps includes a two-dimensional image-based representation of power dissipation within the circuit at a particular instance of time.