High voltage switching regulator with n-channel high-side switches
A circuit. In one aspect, the circuit includes a power input terminal and an output terminal, a high-side circuit coupled between the power input terminal and the output terminal, where the high-side circuit includes a first plurality of serially connected switches, and a low-side circuit coupled between the output terminal and a ground, where the low-side circuit includes a second plurality of serially connected switches, where a first voltage between the power input terminal and the output terminal is distributed across the first plurality of serially connected switches, where a second voltage between the output terminal and the ground is distributed across the second plurality of serially connected switches. In another aspect, the high-side and low-side circuits are arranged to limit a maximum voltage applied to each of the first plurality of switches and second plurality of switches to a fraction of a voltage at the power input terminal.
1. A circuit comprising:
a power input terminal and an output terminal;
a high-side circuit coupled between the power input terminal and the output terminal, wherein the high-side circuit includes a first plurality of serially connected switches; and
a low-side circuit coupled between the output terminal and a ground, wherein the low-side circuit includes a second plurality of serially connected switches;
wherein a first voltage between the power input terminal and the output terminal is distributed across the first plurality of serially connected switches;
wherein a second voltage between the output terminal and the ground is distributed across the second plurality of serially connected switches; and
wherein each of the first plurality of serially connected switches are N-channel metal oxide semiconductor transistors (NMOS) and each of the second plurality of serially connected switches are NMOS transistors, and wherein a drain terminal of a first switch of the second plurality of serially connected switches is connected to the output terminal.
2. The circuit of claim 1 , wherein the high-side circuit and the low-side circuit are arranged to limit a maximum voltage applied to each of the first plurality of serially connected switches and each of the second plurality of serially connected switches to a fraction of a voltage at the power input terminal.
3. The circuit of claim 2 , wherein a value of the fraction is ⅓ or less.
4. The circuit of claim 1 , further comprising a first bootstrap circuit that is arranged to be controlled by a first pair of bootstrap control switches that selectively transition the first bootstrap circuit between a charging configuration that charges the first bootstrap circuit, and a discharging configuration that provides a charge for a turn on of a second switch of the first plurality of serially connected switches.
5. A circuit comprising:
a power input terminal and an output terminal;
a high-side circuit coupled between the power input terminal and the output terminal, wherein the high-side circuit includes a first plurality of serially connected switches;
a low-side circuit coupled between the output terminal and a ground, wherein the low-side circuit includes a second plurality of serially connected switches; and
a high-side driver circuit connected to a gate terminal of a first switch of the first plurality of serially connected switches;
wherein a gate terminal of a second switch of the first plurality of serially connected switches is connected to a drain terminal of the first switch of the first plurality of serially connected switches through a first bootstrap capacitor; and
wherein each of the first plurality of serially connected switches are N-channel metal oxide semiconductor transistors (NMOS) and each of the second plurality of serially connected switches are NMOS transistors, and wherein a drain terminal of a first switch of the second plurality of serially connected switches is connected to the output terminal.
6. The circuit of claim 5 , further comprising a low-side driver circuit connected to a gate terminal of a first switch of the second plurality of serially connected switches.
7. The circuit of claim 6 , wherein a gate terminal of a second switch of the second plurality of serially connected switches is connected to the drain terminal of the first switch of the second plurality of serially connected switches through a second bootstrap capacitor.
8. The circuit of claim 5 , wherein the high-side circuit and the low-side circuit are arranged to limit a maximum voltage applied to each of the first plurality of serially connected switches and each of the second plurality of serially connected switches to a fraction of a voltage at the power input terminal.
9. The circuit of claim 8 , wherein a value of the fraction is ⅓ or less.
10. The circuit of claim 5 , further comprising a first bootstrap circuit that is arranged to be controlled by a first pair of bootstrap control switches that selectively transition the first bootstrap circuit between a charging configuration that charges the first bootstrap circuit, and a discharging configuration that provides a charge for a turn on of the second switch of the first plurality of serially connected switches.
11. A circuit comprising:
a power input terminal and an output terminal;
a high-side circuit coupled between the power input terminal and the output terminal, wherein the high-side circuit includes a first plurality of serially connected switches;
a low-side circuit coupled between the output terminal and a ground, wherein the low-side circuit includes a second plurality of serially connected switches; and
wherein a first voltage between the power input terminal and the output terminal is distributed across the first plurality of serially connected switches;
wherein a second voltage between the output terminal and the ground is distributed across the second plurality of serially connected switches;
a high-side driver circuit connected to a gate terminal of a first switch of the first plurality of serially connected switches;
wherein a gate terminal of a second switch of the first plurality of serially connected switches is connected to a drain terminal of the first switch of the first plurality of serially connected switches through a first bootstrap capacitor; and
wherein each of the first plurality of serially connected switches are N-channel metal oxide semiconductor transistors (NMOS) and each of the second plurality of serially connected switches are NMOS transistors, and wherein a drain terminal of a first switch of the second plurality of serially connected switches is connected to the output terminal.
12. The circuit of claim 11 , wherein the high-side circuit and the low-side circuit are arranged to limit a maximum voltage applied to each of the first plurality of serially connected switches and each of the second plurality of serially connected switches to a fraction of a voltage at the power input terminal.
13. The circuit of claim 12 , wherein a value of the fraction is ⅓ or less.
14. The circuit of claim 11 , further comprising a first bootstrap circuit that is arranged to be controlled by a first pair of bootstrap control switches that selectively transition the first bootstrap circuit between a charging configuration that charges the first bootstrap circuit, and a discharging configuration that provides a charge for a turn on of the second switch of the first plurality of serially connected switches.