Granted Patent B2

US 12,453,084 · App. 17/684,526 · Granted Oct 21, 2025

Inventors: Chiang-Lin Shih (New Taipei, TW); Jhen-Yu Tsai (Kaohsiung, TW); Tseng-Fu Lu (New Taipei, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H10B12/485H10B12/0335

Abstract

Claims (24)

1. A method of manufacturing a semiconductor memory, comprising:

forming a data storage device having a surface;

forming a contact element over the surface of the data storage device and electrically connected to the data storage device, wherein the contact element has a first projecting area vertically projected by the contact element on the surface of the data storage device;

forming a data processing device over the surface of the data storage device and electrically connected to the contact element, wherein a size of the data storage device is greater than a size of the data processing device, wherein the data processing device has a second projecting area vertically projected by the data processing device on the surface of the data storage device, and the second projecting area is non-overlapped with the first projecting area;

disposing a plurality of connection layers on a surface of the data processing device, wherein a first connection layer of the connection layers is electrically connected the contact element with the data processing device; and

disposing a second connection layer, a third connection layer, and a fourth connection layer of the connection layers above the surface of the data storage device, wherein the data processing device comprise a top gate terminal electrically connected to the first connection layer, a drain terminal electrically connected to the second connection layer, a source terminal electrically connected to the third connection layer, and a bottom gate terminal electrically connected to the fourth connection layer.

2. The method of claim 1 , further comprising: forming a capping layer on the surface of the data storage device at a position that the capping layer is formed between the surface of the data storage device and the first connection layer, wherein the contact element extends through the capping layer to electrically couple with the first connection layer.

3. The method of claim 2 , further comprising forming a dielectric layer on the capping layer at a position that the dielectric layer is formed between the capping layer and the first connection layer, wherein the contact element comprises a first contact plug extending through the capping layer to electrically connect with the first connection layer and a second contact plug extending through the dielectric layer, wherein the first contact plug and the second contact plug are electrically connected with each other.

4. The method of claim 3 , wherein the first contact plug is located at the first projecting area and the second contact plug is located above the surface of the data storage device.

5. The method of claim 2 , wherein the capping layer includes silicon dioxide or sapphire, wherein the capping layer is disposed between the data storage device and the data processing device.

6. The method of claim 1 , wherein forming the data processing device is performed at a process temperature less than 400° C.

7. The method of claim 6 , wherein characteristics of the data storage device is immune from the thermal budget of forming the data processing device.

8. The method of claim 5 , wherein forming the data processing device comprises forming a transistor electrically connected to a bit line of the data storage device, wherein the contact element is electrically connected to the bit line of the data storage device.

9. The method of claim 8 , wherein the transistor includes a first gate terminal and a second gate terminal between the capping layer and the first gate terminal of the transistor, and forming the data processing device comprising forming a dielectric layer covering the transistor, wherein the dielectric layer is formed on the capping layer, wherein the second gate terminal is disposed on a top surface of the capping layer and is covered by the dielectric layer.

10. The method of claim 9 , wherein the dielectric layer is formed between the capping layer and the first connection layer, wherein the first connection layer is on the dielectric layer of the data processing device to electrically connect the data processing device to the contact element.

11. The method of claim 1 , wherein forming the data processing device includes forming an IGZO channel and a first gate terminal on the IGZO channel.

12. The method of claim 1 , wherein the data processing device includes one of a silicon-on-insulator (SOI) transistor, an IGZO-based transistor, a Ge-based transistor, or an N-type CMOS pseudo transistor.

13. The method of claim 1 , wherein forming the data storage device comprises forming a capacitor electrically connected to the contact element.

14. The method of claim 13 , wherein forming the data processing device comprises forming a transistor electrically connected to the contact element, wherein the transistor is positioned above the surface of the data storage device and below the first connection layer.

15. The method of claim 8 , wherein the transistor includes an indium gallium zinc oxide (IGZO) channel between the first gate terminal and the second gate terminal.

16. The method of claim 1 , wherein the data processing device overlaps the data storage device in a vertical direction and the contact element overlaps the data storage device in a vertical direction.

17. The method of claim 1 , wherein the data processing device includes one of a silicon-on-insulator (SOI) transistor, an IGZO-based transistor, a Ge-based transistor, or an N-type CMOS pseudo transistor.

18. The method of claim 1 , wherein the data storage device includes a stack of storage dies.

19. The method of claim 1 , wherein the data processing device includes an electrostatic discharge (ESD) protection circuit, and the data processing device includes a programmable computing unit.

Assignments (1)

Continuity (1)

References Cited (28)