Adaptive buffer sharing in multi-core reconfigurable streaming-based architectures
A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.
1 . A hardware accelerator, comprising:
a plurality of functional circuits;
a stream switch; and
a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.
2 . The hardware accelerator of claim 1 , wherein buffer access patterns of the at least one sender core are compatible with buffer access patterns of the at least one receiver core.
3 . The hardware accelerator of claim 1 , wherein the at least one sender core and the at least one receiver core are programmed with dedicated configuration registers to configure the sharing of the buffer content.
4 . The hardware accelerator of claim 1 , wherein the at least one sender core and the at least one receiver core are implemented with In-Memory Computing (IMC) devices.
5 . The hardware accelerator of claim 4 , wherein the at least one sender core has at least one IMC device as the buffer locked in memory mode and has other IMC devices operating in compute mode.
6 . The hardware accelerator of claim 4 , wherein the at least one receiver core has all IMC devices operating in compute mode.
7 . The hardware accelerator of claim 1 , wherein the at least one sender core uses a first subset of the buffer content for computation and the at least one receiver core uses a second subset of the buffer content for computation.
8 . The hardware accelerator of claim 1 , wherein the hardware accelerator is a neural processing unit (NPU).
9 . A system, comprising:
a host device; and
a hardware accelerator, the hardware accelerator including:
a plurality of functional circuits;
a stream switch; and
a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.
10 . The system of claim 9 , wherein buffer access patterns of the at least one sender core are compatible with buffer access patterns of the at least one receiver core.
11 . The system of claim 9 , wherein the at least one sender core and the at least one receiver core are programmed with dedicated configuration registers to configure the sharing of the buffer content.
12 . The system of claim 9 , wherein the at least one sender core and the at least one receiver core are implemented with In-Memory Computing (IMC) devices.
13 . The system of claim 12 , wherein the at least one sender core has at least one IMC device as the buffer locked in memory mode and has other IMC devices operating in compute mode.
14 . The system of claim 12 , wherein the at least one receiver core has all IMC devices operating in compute mode.
15 . The system of claim 9 , wherein the at least one sender core uses a first subset of the buffer content for computation and the at least one receiver core uses a second subset of the buffer content for computation.
16 . The system of claim 9 , wherein the hardware accelerator is a neural processing unit (NPU).
17 . A method, comprising:
streaming data between a plurality of neural network processing cores of a hardware accelerator and a plurality of functional circuits of the hardware accelerator via a stream switch,
wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.
18 . The method of claim 17 , wherein buffer access patterns of the at least one sender core are compatible with buffer access patterns of the at least one receiver core.
19 . The method of claim 17 , wherein the at least one sender core and the at least one receiver core are programmed with dedicated configuration registers to configure the sharing of the buffer content.
20 . The method of claim 17 , wherein the at least one sender core uses a first subset of the buffer content for computation and the at least one receiver core uses a second subset of the buffer content for computation.