Instruction execution method, processor and electronic apparatus
An instruction execution method, a processor and an electronic apparatus. The instruction execution method includes: switching a pipeline architecture of the processor between a first instruction execution mode and a second instruction execution mode according to a selection signal, wherein the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set; the second instruction execution mode supports M threads and is suitable for a second general-purpose register set of the instruction set, the first general-purpose register set is less than the second general-purpose register set, M and N are positive integers, and N is greater than M.
1 . An instruction execution method for a processor, comprising:
switching a pipeline architecture of the processor between a first instruction execution mode and a second instruction execution mode according to a selection signal,
wherein:
the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set, and the second instruction execution mode supports M thread or threads and is suitable for a second general-purpose register set of the instruction set,
the first general-purpose register set is smaller than the second general-purpose register set, M and N are positive integers, and N is greater than M, and
the switching the pipeline architecture of the processor between the first instruction execution mode and the second instruction execution mode according to the selection signal comprises:
in response to a first selection sub-signal for switching from the first instruction execution mode to the second instruction execution mode, combining N first-type register renaming mapping tables for the N threads to obtain M second-type register renaming mapping tables for the M threads, and
in response to a second selection sub-signal for switching from the second instruction execution mode to the first instruction execution mode, splitting the M second-type register renaming mapping tables for the M threads to obtain the N first-type register renaming mapping tables for the N threads,
wherein each of the second-type register renaming mapping tables includes at least two first-type register renaming mapping tables, and the selection signal includes the first selection sub-signal and the second selection sub-signal.
2 . The instruction execution method according to claim 1 , wherein the switching the pipeline architecture of the processor between the first instruction execution mode and the second instruction execution mode according to the selection signal further comprises:
using the selection signal to control a multiplex selection device to perform the switching between the N first-type register renaming mapping tables for the N threads and the M second-type register renaming mapping tables for the M threads.
3 . The instruction execution method according to claim 1 , wherein the first-type register renaming mapping tables and the second-type register renaming mapping tables are each of a random addressed memory architecture.
4 . The instruction execution method according to claim 1 , wherein the first general-purpose register set is a non-extended general-purpose register set of the instruction set, and the second general-purpose register set is an extended general-purpose register set of the instruction set.
5 . The instruction execution method according to claim 4 , wherein the instruction set comprises a complex instruction set or a reduced instruction set.
6 . The instruction execution method according to claim 1 , wherein M is 1, and N is 2, 4, or 8.
7 . The instruction execution method according to claim 6 , wherein a number of general-purpose registers in the first general-purpose register set is ½, ¼, or ⅛ of a number of general-purpose registers in the second general-purpose register set.
8 . A processor, comprising:
a pipeline architecture, and
a switching unit configured to switch the pipeline architecture of the processor between a first instruction execution mode and a second instruction execution mode according to a selection signal,
wherein:
the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set, and the second instruction execution mode supports M thread or threads and is suitable for a second general-purpose register set of the instruction set,
the first general-purpose register set is smaller than the second general-purpose register set, M and N are positive integers, and N is greater than M,
the pipeline architecture comprises N first-type register renaming mapping tables for the N threads, and
switching the pipeline architecture of the processor between the first instruction execution mode and the second instruction execution mode according to the selection signal comprises:
in response to a first selection sub-signal for switching from the first instruction execution mode to the second instruction execution mode, combining N first-type register renaming mapping tables for the N threads to obtain M second-type register renaming mapping tables for the M threads, and
in response to a second selection sub-signal for switching from the second instruction execution mode to the first instruction execution mode, splitting the M second-type register renaming mapping tables for the M threads to obtain the N first-type register renaming mapping tables for the N threads,
wherein each of the second-type register renaming mapping tables includes at least two first-type register renaming mapping tables, and the selection signal includes the first selection sub-signal and the second selection sub-signal.
9 . The processor according to claim 8 , wherein the switching unit comprises a multiplex selection device and is configured to use the selection signal to control the multiplex selection device to perform switching between the N first-type register renaming mapping tables for the N threads and the M second-type register renaming mapping tables for the M threads.
10 . The processor according to claim 8 , wherein the first-type register renaming mapping tables and the second-type register renaming mapping tables are each of a random addressed memory architecture.
11 . The processor according to claim 8 , wherein M is 1, and N is 2, 4, or 8.
12 . The processor according to claim 11 , wherein a number of general-purpose registers in the first general-purpose register set is ½, ¼, or ⅛ of a number of general-purpose registers in the second general-purpose register set.
13 . An electronic apparatus, comprising a processor, and the processor comprising:
a pipeline architecture, and
a switching unit configured to switch the pipeline architecture of the processor between a first instruction execution mode and a second instruction execution mode according to a selection signal,
wherein:
the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set, and the second instruction execution mode supports M thread or threads and is suitable for a second general-purpose register set of the instruction set,
the first general-purpose register set is smaller than the second general-purpose register set, M and N are positive integers, and N is greater than M,
the pipeline architecture comprises N first-type register renaming mapping tables for the N threads, and
switching the pipeline architecture of the processor between the first instruction execution mode and the second instruction execution mode according to the selection signal comprises:
in response to a first selection sub-signal for switching from the first instruction execution mode to the second instruction execution mode, combining N first-type register renaming mapping tables for the N threads to obtain M second-type register renaming mapping tables for the M threads, and
in response to a second selection sub-signal for switching from the second instruction execution mode to the first instruction execution mode, splitting the M second-type register renaming mapping tables for the M threads to obtain the N first-type register renaming mapping tables for the N threads,
wherein each of the second-type register renaming mapping tables includes at least two first-type register renaming mapping tables, and the selection signal includes the first selection sub-signal and the second selection sub-signal.
14 . The electronic apparatus according to claim 13 , wherein the switching unit comprises a multiplex selection device and is configured to use the selection signal to control the multiplex selection device to perform switching between the N first-type register renaming mapping tables for the N threads and the M second-type register renaming mapping tables for the M threads.
15 . The electronic apparatus according to claim 13 , wherein the first-type register renaming mapping tables and the second-type register renaming mapping tables are each of a random addressed memory architecture.
16 . The electronic apparatus according to claim 13 , wherein M is 1, and N is 2, 4, or 8.
17 . The electronic apparatus according to claim 16 , wherein a number of general-purpose registers in the first general-purpose register set is ½, ¼, or ⅛ of a number of general-purpose registers in the second general-purpose register set.