AI-based automated circuit generation method
Disclosed is an AI-based automated circuit generation method. The method includes obtaining design metrics; capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist; simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping until there are no errors in the simulation report, and outputting a final circuit netlist. The present invention solves the problems that the existing method has limitations and is difficult to quickly, automatically and flexibly design a complex circuit.
1 . An AI-based automated circuit generation method, comprising:
obtaining design metrics and storing the design metrics as structured data; wherein the design metrics comprise circuit performance metrics, component metrics, circuit type metrics, and component connection methods;
capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist;
simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and
correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping several times until there are no errors in the simulation report, and outputting a final circuit netlist;
wherein the extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit comprises:
a first-layer Transformer structure, used to extract a local parameter relationship based on the dependency relationship among the design metrics;
a second-layer Transformer structure, used to extract global features based on the local parameter relationship; and
a third-layer Transformer structure, used to extract the overall structure and the high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases;
wherein the obtaining a current circuit netlist comprises:
calculating relevant weights of the design metrics by using normalization operation according to the structured data:
w
i
=
exp
(
s
i
/
T
)
∑
j
exp
(
s
j
/
T
)
wherein w i is a relevant weight of an i th design metric; s i is an initial weight score of a i th design metric; T is a temperature coefficient; s j is an initial weight score of a j th design metric;
calculating a dependency relationship among design metrics by using an attention mechanism:
Attention
(
Q
,
K
,
V
)
=
soft
max
(
Q
K
T
d
k
+
B
)
V
wherein Attention (Q, K, V) is a dependency relationship between a current design metric and all design metrics; soft max is an activation function; Q is a query matrix, which represents the current design metric; K is a key matrix, which is composed of various design metrics; d k is a key dimension; B is a bias term; V is a value matrix, which represents a weight vector related to the design metric; T is transpose;
extracting features by using a multi-layer Transformer structure according to the dependency relationship among design metrics to obtain an overall structure and a high-level feature representation of a circuit;
calculating matching scores of features in the high-level feature representation and embedded representations in the standard circuit netlist template, and extracting embedded representations of which matching scores are greater than a threshold to obtain a matching template set; and
based on the overall structure of the circuit, selecting any one embedded representation from the matching templates of features in the high-level feature representation, and obtaining the current circuit netlist based on the embedded representations selected corresponding to the features.
2 . The AI-based automated circuit generation method according to claim 1 , wherein the extracting a local parameter relationship based on the dependency relationship among the design metrics is specifically as follows:
linearly transforming and positionally encoding structured data to obtain input data extracted from the circuit:
Q
i
n
=
X
W
Q
K
i
n
=
X
W
K
V
in
=
XW
V
wherein Q in is a query vector of input data extracted from the circuit; X is the structured data; W Q , W K and W V are all trainable weight matrices; K in is a key vector of input data extracted from the circuit; V in is a value vector of input data extracted from the circuit; and
inputting the input data extracted from the circuit into a multi-head self-attention mechanism to obtain the local parameter relationship; wherein a bias term of the multi-head self-attention mechanism of the first-layer Transformer structure is the dependency relationship among design metrics.
3 . The AI-based automated circuit generation method according to claim 1 , wherein an expression for the global feature is as follows:
H
2
′
=
LayerNorm
(
H
2
+
FFN
(
H
2
)
)
H
2
=
LayerNorm
(
H
1
+
Atte
ntion
(
H
1
W
1
Q
,
H
1
W
1
K
,
H
1
W
1
V
)
)
wherein H 2 ′ is the global feature; LayerNorm is layer normalization operation; H 2 is an intermediate representation; FFN is a feedforward neural network; H 1 is the local parameter relationship; and
W
1
Q
,
W
1
K
and
W
1
V
are all trainable weight matrices that map data to vectors.
4 . The AI-based automated circuit generation method according to claim 1 , wherein an expression for the overall structure and the high-level feature representation of the circuit is as follows:
S
=
f
struct
(
H
final
)
=
σ
(
W
s
·
H
fused
+
b
s
)
H
final
=
Concat
(
H
2
′
,
E
h
i
s
t
)
W
fusion
F
=
f
feat
(
H
final
)
=
MLP
(
GlobalAvgPool
(
H
final
)
)
=
W
f
·
(
1
n
∑
i
=
1
n
H
final
(
i
)
)
+
b
f
wherein S is the overall structure of the circuit; f struct is a structure generation function; H final is a final fused hidden state; σ is an activation function; W s is a structure mapping matrix used to project a high-dimensional feature space into a structure label space; H fused is a circuit feature representation that combines structural semantics of a current circuit state and a historical circuit template; b s is a bias vector; Concat is connection operation; H 2 ′ is the global feature; E hist is historical circuit encoding; W fusion is a fusion weight matrix; F is a high-level feature representation; f feat is a high-dimensional feature mapping function used to extract key design features from the final fused hidden state H final ; MLP is a high-dimensional mapping layer; GlobalAvgPool is global average pooling; W f is a weight of the high-dimensional mapping layer; n is a number of structural units in the circuit;
H
final
(
i
)
is a final feature sequence after fusion; and b f is a bias of the high-dimensional mapping layer.
5 . The AI-based automated circuit generation method according to claim 1 , wherein an expression for the matching score is as follows:
s
i
1
j
1
=
cos
(
f
i
1
,
t
j
1
)
=
f
i
1
·
t
j
1
f
i
1
·
t
j
1
wherein s i 1 j 1 is a matching score between f i 1 and t j 1 ; COS is a cosine similarity calculation function; f i 1 is an i 1 th feature of the high-level feature representation; t j 1 is a j 1 th embedding representation; and ⋅ is the norm of the vector.
6 . The AI-based automated circuit generation method according to claim 1 , wherein the error information comprises error type and error location.
7 . The AI-based automated circuit generation method according to claim 6 , wherein the correcting the current circuit netlist based on the error information is specifically as follows:
based on the error location, finding a corresponding node and taking a preset correction action based on the error type.