DC-to-DC converter with pulse skipping function and on-time control function, and electronic devices including the same
Disclosed is a DC-to-DC converter which includes a first switching circuit connected between a power line receiving a DC voltage and an output terminal of the DC-to-DC converter and switched based on a first pulse control signal, a second switching circuit connected between the output terminal and a ground and switched based on a second pulse control signal, a pulse control signal generation circuit that receives a first level of a first voltage associated with an output voltage and a second level of a first reference voltage, wherein, in response to the second level being higher than the first level, the pulse control signal generation circuit is configured to generate the first pulse control signal to increase the output voltage and wherein, in response to the second level being lower than the first level, the pulse control signal generation circuit is configured to generate the second pulse control signal.
1 . A DC-to-DC converter comprising:
a first switching circuit connected between a power line receiving a DC voltage and an output terminal of the DC-to-DC converter, and the first switching circuit configured to be switched based on a first pulse control signal;
a second switching circuit connected between the output terminal and a ground, and the second switching circuit configured to be switched based on a second pulse control signal;
a pulse control signal generation circuit configured to,
receive a first level of a first voltage associated with an output voltage of the output terminal and a second level of a first reference voltage,
generate the first pulse control signal to increase the output voltage, in response to the second level of the first reference voltage being higher than the first level of the first voltage associated with the output voltage of the output terminal,
generate the second pulse control signal to decrease the output voltage, in response to the second level of the first reference voltage being lower than the first level of the first voltage associated with the output voltage of the output terminal, and
set a pulse skip mode control signal to a first mode, in response to a zero current detection signal not occurring within a reference cycle; and
a pulse skip control circuit configured to selectively transfer the second pulse control signal to the second switching circuit based on the zero current detection signal and the pulse skip mode control signal such that the second pulse control signal is transferred to the second switching circuit to decrease the output voltage, in response the pulse skip mode control signal being set to the first mode, and
wherein the first pulse control signal and the second pulse control signal are complementary signals.
2 . The DC-to-DC converter of claim 1 , wherein the pulse control signal generation circuit includes
a first comparator configured to compare the first level and the second level and to output a first comparison voltage, and
an SR latch including a set input terminal configured to receive the first comparison voltage, a reset input terminal configured to receive an on-time control signal for controlling a pulse width of the first pulse control signal, an output terminal configured to output the first pulse control signal, and an inverse output terminal configured to output the second pulse control signal.
3 . The DC-to-DC converter of claim 2 , further comprising:
a second comparator including a first input terminal, a second input terminal configured to receive a second reference voltage, and an output terminal configured to generate the on-time control signal;
a first current supply circuit configured to supply a first current to the first input terminal in response to a mode control signal;
a second current supply circuit configured to supply a second current to the first input terminal in response to the pulse skip mode control signal; and
a capacitor connected between the first input terminal and the ground,
wherein an amount of the second current is more than or less than an amount of the first current.
4 . The DC-to-DC converter of claim 1 , wherein the pulse skip control circuit includes
a first AND gate configured to receive the zero current detection signal and an inverted pulse skip mode control signal, and
a second AND gate configured to determine whether to transfer the second pulse control signal to the second switching circuit, based on an inverted version of an output signal of the first AND gate.
5 . The DC-to-DC converter of claim 4 , further comprising:
a zero current sensor configured to generate the zero current detection signal of a third level in response to a level of the output voltage being equal to or higher than a ground voltage and to generate the zero current detection signal of a fourth level in response to the first pulse control signal transitioning to the third level, the fourth level being lower than the third level.
6 . The DC-to-DC converter of claim 4 , further comprising:
a first comparator configured to compare a level of the output voltage and a ground voltage; and
a D-flip-flop including an input terminal configured to receive a voltage of a high level, a clock terminal connected with an output terminal of the first comparator, a reset terminal configured to receive the first pulse control signal, and an output terminal configured to output the zero current detection signal.
7 . The DC-to-DC converter of claim 6 , further comprising:
a de-glitch circuit configured generate a de-glitch zero current detection signal by delaying the zero current detection signal as much as a de-glitch delay time;
a second comparator configured to compare a level of a negative reference voltage and the level of the output voltage;
a delay circuit configured to delay the second pulse control signal;
a third AND gate configured to receive an output signal of the second comparator and an output signal of the delay circuit; and
a fourth AND gate configured to perform an AND operation on an output signal of the third AND gate and the pulse skip mode control signal to output a voltage detection signal.
8 . The DC-to-DC converter of claim 7 , wherein the pulse skip control circuit is configured to prevent the second pulse control signal from being transferred to the second switching circuit in response to the zero current detection signal of a third level, which is generated in response to the level of the output voltage being higher than the ground voltage and the pulse skip mode control signal of a fourth level, the fourth level being lower than the third level.
9 . The DC-to-DC converter of claim 7 , further comprising:
a mode detector configured to receive the zero current detection signal output from the D-flip flop, the de-glitch zero current detection signal output from the de-glitch circuit, and the voltage detection signal, and the mode detector configured to determine whether to activate the pulse skip mode control signal based on whether the zero current detection signal continues to toggle, a result of comparing a time corresponding to a pulse width of the zero current detection signal and the de-glitch delay time, and whether the voltage detection signal continues to toggle.
10 . A power management integrated circuit comprising:
a semiconductor substrate; and
the DC-to-DC converter of claim 1 integrated on the semiconductor substrate.
11 . An electronic device comprising:
a power management integrated circuit including a DC-to-DC converter including an output terminal and a feedback voltage terminal;
a load configured to filter an output voltage output from the output terminal and to generate a filtered voltage; and
a device configured to be powered by the filtered voltage,
wherein the DC-to-DC converter includes
a first switching circuit connected between a power line receiving a DC voltage and the output terminal, wherein the first switching circuit is configured to be switched based on a first pulse control signal;
a second switching circuit connected between the output terminal and a ground, wherein the second switching circuit is configured to be switched based on a second pulse control signal;
a pulse control signal generation circuit configured to,
receive a first level of a first voltage associated with the output voltage and a second level of a first reference voltage,
generate the first pulse control signal to increase the output voltage, in response to the second level of the first reference voltage being higher than the first level of the first voltage associated with the output voltage of the output terminal, and
generate the second pulse control signal to decrease the output voltage, in response to the second level of the first reference voltage being lower than the first level of the first voltage associated with the output voltage of the output terminal, and
set a pulse skip mode control signal to a first mode, in response to a zero current detection signal not occurring within a reference cycle; and
a pulse skip control circuit configured to selectively transfer the second pulse control signal to the second switching circuit based on the zero current detection signal and the pulse skip mode control signal such that the second pulse control signal is transferred to the second switching circuit to decrease the output voltage, in response the pulse skip mode control signal being set to the first mode, and
wherein the first pulse control signal and the second pulse control signal are complementary signals.
12 . The electronic device of claim 11 , wherein the pulse control signal generation circuit includes
a first comparator configured to compare the first level and the second level and to output a first comparison voltage, and
an SR latch including a set input terminal configured to receive the first comparison voltage, a reset input terminal configured to receive an on-time control signal for controlling a pulse width of the first pulse control signal, an output terminal configured to output the first pulse control signal, and an inverse output terminal configured to output the second pulse control signal.
13 . The electronic device of claim 12 , wherein the DC-to-DC converter further comprises
an emulator configured to emulate an inductor current flowing through an inductor included in the load by using the output voltage and to generate an emulation voltage including a ripple, and
an adder circuit configured to generate the first voltage by adding a feedback voltage fed back from the load through the feedback voltage terminal and the emulation voltage.
14 . The electronic device of claim 12 , wherein the DC-to-DC converter further comprises
a second comparator including a first input terminal, a second input terminal receiving a second reference voltage, and an output terminal outputting the on-time control signal,
a first current supply circuit configured to supply a first current to the first input terminal in response to a mode control signal,
a second current supply circuit configured to supply a second current to the first input terminal in response to the pulse skip mode control signal, and
a capacitor connected between the first input terminal and the ground,
wherein an amount of the second current is more than or less than an amount of the first current.
15 . The electronic device of claim 11 , wherein the pulse skip control circuit includes
a first AND gate configured to receive the zero current detection signal and an inverted pulse skip mode control signal, and
a second AND gate configured to determine whether to transfer the second pulse control signal to the second switching circuit, based on an inverted version of an output signal of the first AND gate.
16 . The electronic device of claim 15 , wherein the DC-to-DC converter further comprises
a zero current sensor configured to generate the zero current detection signal of a third level in response to a level of the output voltage being equal to or higher than a ground voltage and to generate the zero current detection signal of a fourth level in response to the first pulse control signal transitioning to the third level, the fourth level being lower than the third level.
17 . The electronic device of claim 11 , further comprising:
a DC voltage generator configured to generate the DC voltage,
wherein the electronic device is a mobile device, and
wherein the device is a system on chip.
18 . The electronic device of claim 11 , further comprising:
a controller configured to control an operation of the device,
wherein the electronic device is a memory module, and
wherein the device is a volatile memory device or a nonvolatile memory device and the controller is a memory controller.
19 . An operating method of a DC-to-DC converter which includes a first switching circuit connected between a power line receiving a DC voltage and an output terminal and switched based on a first pulse control signal and a second switching circuit connected between the output terminal and a ground and switched based on a second pulse control signal, the method comprising:
generating the first pulse control signal for increasing the output voltage, in response to a first voltage associated with an output voltage of the output terminal being smaller than a first reference voltage;
generating the second pulse control signal for decreasing the output voltage, in response to the first voltage being greater than the first reference voltage;
setting a pulse skip mode control signal to a first mode, in response to a zero current detection signal not occurring within a reference cycle; and
selectively transferring the second pulse control signal to the second switching circuit, based on the zero current detection signal and the pulse skip mode control signal such that the second pulse control signal is transferred to the second switching circuit to decrease the output voltage, in response the pulse skip mode control signal being set to the first mode,
wherein the first pulse control signal and the second pulse control signal are complementary signals.
20 . The method of claim 19 , wherein the determining whether to transfer the second pulse control signal to the second switching circuit includes
generating the zero current detection signal of a first level in response to the output voltage being equal to a ground voltage,
inverting the pulse skip mode control signal of a second level to generate the pulse skip mode control signal of the first level, the second level being lower than the first level,
generating a first AND signal by performing an AND operation on the zero current detection signal of the first level and the pulse skip mode control signal of the first level,
inverting the first AND signal to generate an inverted first AND signal, and
preventing the second pulse control signal from being transferred to the second switching circuit based on a result of performing an AND operation on the second pulse control signal and the inverted first AND signal.