Insulated gate semiconductor device
A semiconductor device includes: a high-concentration layer of a first conductivity-type provided on a drift layer of the first conductivity-type; a buried layer of a second conductivity-type provided in the high-concentration layer; an injection regulation region of the second conductivity-type provided on the high-concentration layer; a high-concentration region of the second conductivity-type provided inside the injection regulation region; a carrier supply region of the first conductivity-type provided at an upper part of the injection regulation region; and an insulated gate structure provided inside a trench, wherein a ratio of the impurity concentration of the injection regulation region to an impurity concentration of an upper part of the high-concentration layer is 0.5 or greater and 2 or smaller.
1 . An insulated gate semiconductor device comprising:
a drift layer of a first conductivity-type;
a high-concentration layer of the first conductivity-type, and including:
a lower region on a top surface of the drift layer, and
an upper region on a top surface of the lower region and having an impurity concentration lower than an impurity concentration of the lower region;
a buried layer of a second conductivity-type inside the high-concentration layer and including an upper buried region inside the upper region;
an injection regulation region of the second conductivity-type on a top surface of the upper region and a top surface of the upper buried region;
a high-concentration region of the second conductivity-type inside the injection regulation region and having an impurity concentration higher than an impurity concentration of the injection regulation region;
a carrier supply region of the first conductivity-type selectively at an upper part of the injection regulation region;
a plurality of trenches, a trench among the plurality of trenches penetrating the injection regulation region to reach the high-concentration layer; and
an insulated gate structure inside the trench,
wherein
a ratio of the impurity concentration of the injection regulation region to an impurity concentration of the high-concentration layer at least at a part in the upper region of the high-concentration layer in contact with the injection regulation region is 0.5 or greater and 2 or smaller,
the high-concentration region has both side surfaces directly in contact with adjacent trenches among the plurality of trenches, and
the high-concentration region is evenly in a middle in a depth direction of the injection regulation region.
2 . The insulated gate semiconductor device of claim 1 , wherein the impurity concentration of the high-concentration layer at least at the part in contact with the injection regulation region is 4×10 16 cm −3 or greater and 6×10 16 cm −3 or less.
3 . The insulated gate semiconductor device of claim 1 , wherein the impurity concentration of the part is 4×10 16 cm −3 or greater and 5×10 16 cm −3 or less, and the ratio of the impurity concentration is 0.5 or greater and 1 or smaller.
4 . The insulated gate semiconductor device of claim 1 , wherein the impurity concentration of the part is 5×10 16 cm −3 or greater and 6×10 16 cm −3 or less, and the ratio of the impurity concentration is 1.2 or greater and 2 or smaller.
5 . The insulated gate semiconductor device of claim 1 , wherein the buried layer further includes
a lower buried region inside the lower region, and
the upper buried region is at a part of a top surface of the lower buried region and separated from the trench.
6 . The insulated gate semiconductor device of claim 5 , further comprising a partial current spreading layer of the first conductivity-type at a part of a bottom surface of the lower buried region and having an impurity concentration higher than an impurity concentration of the drift layer.
7 . The insulated gate semiconductor device of claim 5 , wherein another part of the lower buried region is in contact with a bottom surface of the trench.
8 . The insulated gate semiconductor device of claim 5 , wherein a depth of a bottom surface of the lower region is greater than a depth of a bottom surface of the lower buried region.
9 . The insulated gate semiconductor device of claim 1 , wherein the impurity concentration of the high-concentration region is 2×10 17 cm −3 or greater and 7×10 17 cm −3 or less.
10 . The insulated gate semiconductor device of claim 1 , wherein a bottom surface of the upper region of the high-concentration layer is in contact with a side wall of the trench.
11 . The insulated gate semiconductor device of claim 5 , wherein
the lower buried region includes a plurality of lower buried regions, and
a bottom surface of each trench of the plurality of trenches is directly in contact with a top surface of a lower buried region of the plurality of lower buried regions.
12 . The insulated gate semiconductor device of claim 11 , wherein lower buried regions of the plurality of lower buried regions are separated from each other with upper parts of the lower region interposed therebetween.
13 . The insulated gate semiconductor device of claim 12 , wherein lower buried regions of the plurality of lower buried regions are in a middle position between adjacent trenches of the plurality of trenches.
14 . The insulated gate semiconductor device of claim 5 , wherein the upper region is on a top surface of the lower buried region.
15 . The insulated gate semiconductor device of claim 1 , wherein side surfaces of the upper buried region are directly in contact with upper regions.