IP Library Granted Patent US 12,464,833
Granted Patent B2
US 12,464,833 · App. 17/984,564 · Granted Nov 4, 2025

Avalanche photodetectors with a combined lateral and vertical arrangement

Inventors: Khee Yong Lim (Singapore, SG); Kian Ming Tan (Singapore, SG); Kiok Boone Elgin Quek (Singapore, SG)
Assignee: GlobalFoundries Singapore Pte. Ltd.
H10F30/2255H10F71/121H10F77/122H10F77/206
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Quick Facts
Patent No.
US 12,464,833
App. No.
17/984,564
Granted
Nov 4, 2025
Kind
B2
Abstract

Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure comprises a substrate having a first conductivity type, a first semiconductor layer that defines an absorption region of the avalanche photodetector, a dielectric layer between the first semiconductor layer and the substrate, a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer, and a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate. The second semiconductor layer defines a multiplication region of the avalanche photodetector.

Claims (36)

1 . A structure for an avalanche photodetector, the structure comprising:

a substrate having a first conductivity type;

a first semiconductor layer that defines an absorption region of the avalanche photodetector;

a first contact connected to the substrate;

a second contact connected to a side edge portion of the first semiconductor layer;

a dielectric layer between the first semiconductor layer and the substrate;

a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer; and

a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate,

wherein the second semiconductor layer defines a multiplication region.

2 . The structure of claim 1 wherein the first semiconductor layer is intrinsic germanium.

3 . The structure of claim 1 wherein the second semiconductor layer is intrinsic silicon.

4 . The structure of claim 1 wherein the semiconductor material is silicon, the first conductivity type is n-type, and the second conductivity type is p-type.

5 . The structure of claim 1 wherein the charge control region is a third semiconductor layer including a first portion that is surrounded by the first semiconductor layer.

6 . The structure of claim 5 wherein the first portion of the third semiconductor layer has a first interface with the first semiconductor layer and a second interface with the second semiconductor layer.

7 . The structure of claim 6 wherein the first interface is oriented substantially orthogonal to the second interface.

8 . The structure of claim 5 wherein the third semiconductor layer includes a second portion that projects above the first semiconductor layer.

9 . The structure of claim 5 wherein the second semiconductor layer and the third semiconductor layer are arranged in a vertical layer stack.

10 . The structure of claim 1 wherein the dielectric layer adjoins the substrate along an interface, and the second semiconductor layer includes a first portion arranged above the interface.

11 . The structure of claim 10 wherein the second semiconductor layer includes a second portion arranged below the interface.

12 . The structure of claim 1 wherein the charge control region is a doped region in the second semiconductor layer.

13 . The structure of claim 12 wherein the second semiconductor layer includes a portion positioned between the doped region and the first semiconductor layer.

14 . The structure of claim 13 wherein the portion of the second semiconductor layer surrounds the doped region.

15 . The structure of claim 1 wherein the charge control region is surrounded by the first semiconductor layer.

16 . The structure of claim 1 wherein the substrate, the dielectric layer, and the first semiconductor layer define a layer stack of a germanium-on-insulator substrate.

17 . The structure of claim 1 wherein the semiconductor material is silicon, and the first semiconductor layer is intrinsic germanium.

18 . A method of forming a structure for an avalanche photodetector, the method comprising:

providing a substrate having a first conductivity type, a first semiconductor layer, and a dielectric layer between the first semiconductor layer and the substrate;

patterning the first semiconductor layer to define an absorption region of the avalanche photodetector;

forming a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer;

forming a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate, wherein the second semiconductor layer defines a multiplication region of the avalanche photodetector;

forming a first contact connected to the substrate; and

forming a second contact connected to a side edge portion of the first semiconductor layer.

19 . The method of claim 18 wherein forming the charge control region comprising the semiconductor material having the second conductivity type opposite to the first conductivity type comprises:

epitaxially growing a third semiconductor layer on the second semiconductor layer.

20 . The method of claim 18 wherein forming the charge control region comprising the semiconductor material having the second conductivity type opposite to the first conductivity type comprises:

forming a doped region in the second semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2022
From: LIM, KHEE YONG; TAN, KIAN MING; QUEK, KIOK BOONE ELGIN
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 061720/0776 →
Continuity (1)
Related Publication 20240162365A1 · May 16, 2024
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