IP Library Granted Patent US 12,468,537
Granted Patent B2
US 12,468,537 · App. 17/575,563 · Granted Nov 11, 2025

Location agnostic data access

Inventors: Maciej Marcin Piechotka (San Jose, CA); Kyrylo Perelygin (Broomfield, CO); Ze Long (San Jose, CA); Raphael Dominique Pierre Boissel (San Jose, CA); Michael Murphy (Newark, CA); Anis Ladram (Zurich, CH); Isaac Gelado (Pacifica, CA); Girish Bhaskarrao Bharambe (Pune, IN); Sebastian Piotr Jodlowski (San Jose, CA)
Assignee: NVIDIA Corporation
G06F9/3822G06F9/3851G06F9/3879G06F9/3888G06F9/545G06F13/1663
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,468,537
App. No.
17/575,563
Granted
Nov 11, 2025
Kind
B2
Abstract

Apparatuses, systems, and techniques to enable a program to access data regardless of where said data is stored. In at least one embodiment, a system enables a program to access data regardless of where said data is stored, based on, for example, one or more locations encoding one or more addresses of said data.

Claims (40)

1 . A processor, comprising:

one or more circuits to cause two or more software programs to access a same physical storage location based, at least in part, on a common index used in one or more physical storage tables of each of the two or more software programs to indicate one or more entries within one or more physical storage tables.

2 . The processor of claim 1 , wherein the one or more circuits are further to:

obtain source code of the two or more software programs; and

enable the two or more software programs to access data of the physical storage location regardless of where the data is stored by at least compiling the source code to executable code that indicates one or more locations corresponding to the data.

3 . The processor of claim 2 , wherein the one or more locations are stored in constant memory.

4 . The processor of claim 2 , wherein the one or more locations encode one or more addresses of data.

5 . The processor of claim 1 , wherein the two or more software programs are is executable by one or more graphics processing units (GPUs).

6 . The processor of claim 1 , wherein the one or more circuits are further to execute the two or more software programs by at least obtaining data of the physical storage location based on one or more locations encoding one or more addresses of the data regardless of where the data is stored relative to other data.

7 . The processor of claim 1 , wherein the two or more software programs encode one or more kernels.

8 . A system, comprising:

one or more computers having one or more processors to cause two or more software programs to access a same physical storage location based, at least in part, on a common index used in one or more physical storage tables of each of the two or more software programs to indicate one or more entries within one or more physical storage tables.

9 . The system of claim 8 , wherein the one or more processors are further to generate assembly code based at least in part on code of the two or more software programs, wherein the assembly code is generated to use a same memory location in a constant memory bank regardless of where data of the physical storage location is stored.

10 . The system of claim 9 , wherein the assembly code encodes one or more locations corresponding to the data to indicate one or more addresses of where the data is stored.

11 . The system of claim 8 , wherein the one or more processors are further to cause the two or more software programs to:

generate a current address of data of the physical storage location after the data has moved to a new memory location;

obtain the current address of the data by using one or more indicators stored in a constant memory bank; and

access the data using the current address.

12 . The system of claim 8 , wherein the two or more software programs access data of the physical storage location based at least in part on one or more addresses stored in one or more registers.

13 . The system of claim 8 , wherein data of the physical storage location includes at least one of: image data, video data, and audio data.

14 . The system of claim 8 , wherein the two or more software programs is are executable by one or more general purpose graphics processing units (GPGPUs).

15 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:

cause two or more software programs to access a same physical storage location based, at least in part, on a common index used in one or more physical storage tables of each of the two or more software programs to indicate one or more entries within one or more physical storage tables.

16 . The machine-readable medium of claim 15 , wherein the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to access data of the physical storage location using one or more addresses of the data stored in one or more registers.

17 . The machine-readable medium of claim 15 , wherein data of the physical storage location includes one or more components of a library.

18 . The machine-readable medium of claim 15 , wherein the two or more software programs indicate data of the physical storage location through one or more locations in a register corresponding to the data.

19 . The machine-readable medium of claim 18 , wherein the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to:

obtain another program that indicates the data; and

enable the other program to access the data by at least causing the other program to indicate how to access the data through the one or more locations in the register corresponding to the data.

20 . The machine-readable medium of claim 15 , wherein data of the physical storage location includes one or more data objects.

21 . The machine-readable medium of claim 15 , wherein the two or more software programs is are executable by one or more parallel processing units (PPUs).

22 . A method, comprising:

causing two or more software programs to access a same physical storage location based, at least in part, on a common index used in one or more physical storage tables of each of the two or more software programs to indicate one or more entries within one or more physical storage tables.

23 . The method of claim 22 , further comprising generating executable code based at least in part on source code, wherein the executable code encodes one or more locations in memory that comprise a first set of addresses corresponding to a first set of memory locations of data of the physical storage location.

24 . The method of claim 23 , further comprising:

transferring the data to a second set of memory locations; and

updating the one or more locations in the memory to comprise a second set of addresses corresponding to the second set of memory locations.

25 . The method of claim 22 , wherein the two or more software programs access data of the physical storage location based on a register that indicates an actual location of the data.

26 . The method of claim 22 , further comprising executing a plurality of programs that utilize data of the physical storage location, wherein the plurality of programs indicate the data through one or more locations that encode one or more addresses of the data.

27 . The method of claim 22 , wherein data of the physical storage location includes one or more data structures.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2022
From: PIECHOTKA, MACIEJ MARCIN; PERELYGIN, KYRYLO; LONG, ZE; BOISSEL, RAPHAEL DOMINIQUE PIERRE; MURPHY, MICHAEL; LADRAM, ANIS; GELADO, ISAAC; BHARAMBE, GIRISH BHASKARRAO; JODLOWSKI, SEBASTIAN PIOTR
To: NVIDIA CORPORATION
Reel/Frame 059212/0625 →
Continuity (1)
Related Publication 20230221960A1 · Jul 13, 2023
References Cited (7)
US 11620233B1 · Habusha · 2023 [cited by examiner]
US 20150378908A1 · Gschwind · 2015 [cited by examiner]
US 20190146817A1 · Tirumala · 2019 [cited by examiner]
Anonymous, “Addressing Mode—Wikipedia,” retrieved from https://en.wikipedia.org/w/index.php?title=Addressing_mode&oldid=1062042351, Dec. 25, 2021, 16 pages. [cited by applicant]
IEEE, “IEEE Standard 754-2008 (Revision of IEEE Standard 754-1985): IEEE Standard for Floating-Point Arithmetic,” Aug. 29, 2008, 70 pages. [cited by applicant]
International Search Report and Written Opinion for Application No. PCT/US2023/060683, mailed Apr. 11, 2023, filed Jan. 13, 2023, 13 pages. [cited by applicant]
TIS Committee, “Tool Interface Standard (TIS) Executable and Linking Format (ELF) Specification,” Tis Committee, Version 1.2, May 1995, 106 pages. [cited by applicant]